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Participant
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Registered: ‎07-23-2010

Problem with Floating Point IP Core

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Hello everybody,

 

I am trying to convert an integer signal in a double one by using the Floating Point Operator IP Core (provided by Coregen), v5.0. But, in spite of correctly inserting the values to this core, it never asserts the RDY signal (see diagram.jpg figure)... I have realized that if I keep the operation_nd asserted while it is working then it finally asserts RDY, but my problem is that the operation_nd signal is assigned another signal from another module that only lasts one clock cycle, so it is impossible to have it working correctly. The example provided in the documentation shows operation_nd active for just one clock cycle... (see example_diagram.jpg).

 

diagram.jpg

 

example_diagram.jpg

 

 

I have tried with Behavioural and Structural simulations, and different latency configurations, but the problem remains...

 

Is there any problem with this core??

 

Thanks in advance!

 

EDIT: I have tried also asserting the CE signal and nothing...

Alejandro Cristo
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Participant
Participant
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Registered: ‎07-23-2010

Ey guys,

 

i've just found the problem. I asserted the operation_nd signal when clock was 0, instead of 1. Asserting this signal when clock rises fixes the problem.

 

Thanks anyway!

Alejandro Cristo

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Highlighted
Participant
Participant
2,887 Views
Registered: ‎07-23-2010

Ey guys,

 

i've just found the problem. I asserted the operation_nd signal when clock was 0, instead of 1. Asserting this signal when clock rises fixes the problem.

 

Thanks anyway!

Alejandro Cristo

View solution in original post

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