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Registered: ‎05-18-2015

Problems creating TMR microblaze with common (shared) local memory

I am trying to implement a triple modular redundant (TMR) Microblaze according to Xilinx document PG268. I am starting from a working microblaze project that has been working on hardware for several months.

The TMR block automation wizard has an two options for the local memory:

"Local to triplicate the local memory for the best possible error detection, or select Common with ECC to use a common local memory with error correcting codes to reduce block RAM use."

My target device does not have enough RAM to triplicate the local memory without reducing the size of the local RAM.   Therefore I need to use the common (shared) local memory option.

I cannot get the "Common with ECC" option to produce a valid design on its own.   If I include the local memory in the microblaze's hierarchical block before I run the wizard, then the local memory gets triplicated regardless of the setting I choose for the LMB block ram type.   If I exclude the local memory from the hierarchical block, then the design always fails synthesis with errors. The TMR manager has a number of registers inside which connect to the processor over the LMB.   The block automation wizard seems to have trouble connecting both a shared local memory and the TMR manager to the microblaze LMB.   


The closest that I have gotten it to work is to ungrounp the hierarchy for the microblaze local memory, and then group the microblaze with the LMB interface and the LMB BRAM interface modules like this:




Note that the AXI interconnect has to be there to connect the microblaze to the AXI bus on the LMB BRAM controller when ECC is enabled.  I have another AXI interconnect at the top level block design to connect to all of my AXI peripherals.  The second AXI interconnect is connected the M00 port of the AXI interconnect inside the microblaze hierarchy.    (I have never tried to cascade AXI interconnects before, but the tool seems to be handling this part of the design OK)


If I then run the TMR wizard on this architecture (BRAM outside the microblaze's hierarchical block, BRAM controllers inside the hierarchical block) then the TMR wizard seems to produce a valid design with a shared memory with ECC..... but it requires a lot of manual setup on my part.   I also cannot get Vivado to initialize the BRAM with an ELF file.  


I get the following error when I try to generate a bitfile from the TMR design:

[Memdata 28-96] Could not find a BMM_INFO_DESIGN property in the design. Could not generate the merged BMM file



Has anyone else successfully used the "Common with ECC" option to generate a common BRAM with ECC?  If so, what did your microblaze hierarchy block look like before you ran the TMR wizard?   Were the LMB, LMB BRAM controller, and BRAM all inside the hierarchy block?  I certainly feel like I am fighting the tool to get my design to turn out the way that I want it.


How can I fix the "Could not find a BMM_INFO_DESIGN property in the design" error so that I can generate a bitfile?


Is there any documentation or training material available on the TMR microblaze other than PG268?


Any advice or lessons-learned regarding the TMR Microblaze would be greatly appreciated.

Tool version: Vivado 2018.3, Target device: XC7K160


Update:  I have confirmed that the same problems occur in 2018.3 and 2019.2.









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3 Replies
Registered: ‎05-18-2015

The other error message that I get when I try to generate a bitfile for the TMR design is:


[BD 41-1273] Error running post_propagate TCL procedure: can't read "suffix": no such variable
::xilinx.com_ip_tmr_comparator_1.0::post_propagate Line 31



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Registered: ‎04-17-2011

@davidsummers Sharing the resolution for the wider community.

When we create the non-TMR Microblaze design, please follow the steps below:

  1. Build the non-TMR Microblaze design in Vivado IPI
  2. Create a hierarchy with only Microblaze IP and the AXI Peripheral if any in it. Do not include MDM, Proc Sys Reset, Clock gen, LMB in it.
  3. Add the TMR Manager inside the above hierarchy.
  4. Run block automation, set “LMB Memory Configuration” to “Common With ECC” and “SEM Interface” to “None”

This should generate the configuration (Common with ECC) which is being discussed in this thread. I hope that helped you move forward with your design.

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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Registered: ‎06-27-2018

Hello Sir, thanks for your help

I would like to follow up on this issue :

I managed to create a TMR Microblaze design with local Bram.

To reduce BRAM utilisation, I am trying the procedure you detailed to use common BRAMs with ECC

However I got the following errors :

ERROR: [BD 41-703] Peripheral </HR/MB2/tmr_manager_0/SLMB/Reg> is mapped into master segment </HR/MB2/mb/Data/SEG_tmr_manager_0_Reg>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.
ERROR: [BD 41-703] Peripheral </HR/MB3/tmr_manager_0/SLMB/Reg> is mapped into master segment </HR/MB3/mb/Data/SEG_tmr_manager_0_Reg>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

As a workaround, I had to remove unconnected slaves in the Address Editor(see the pictures attached), and now each microblaze only the same slave interface of tmr_manager

Is it the right way to proceed ?  I provide also the tcl script for generating the triplicated microblaze system

Best regards

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