In my design, I've got two AXI domains, one running at 91 MHz (long story...) and one running at 125 MHz.
I've instantiated two PSR blocks to produce resets for these two domains. The two blocks are connected to the same inputs, except that the slowest_sync_clock for each is connected to the AXI clock for the appropriate domain.
We had a bug, which was that the ext_reset_in pins on the two blocks were different polarity. Can you see the bubble? That's the bug!
It's not possible to change the input polarity, as it's automatically determined. We can't figure out how it's automatically determined, as both blocks were previously connected to the same constant IP block.
Obviously, we've worked around this by having two constant blocks, one driving a zero into one of these and the other driving a one.
The problems shows up in Vivado 2016.2.
In Vivado 2018.1, it is possible to set the input polarity of both ext_reset_in and aux_reset_in, so there is no problem.
When I searched, I didn't find a note of a bugfix. I just wanted to make a public note of this because it cost us a couple of hours.
There are two thing that you can do to get rid of this problem:
1. Connect both ext-reset-in pins in both PSR IPs to the external reset of the FPGA (reset) and constranthis pin in your XDC file.
2. Do click on the ext_reset_pin of the PSR and in the left window entitled Block Pin Properrtiesopen expand the CONFIG and you'll see a pencil marker beside the POLARITY option. Click on the Pencil and write ACTIVE_HIGH and press enter to save it.
If you re-implement the design it should work.
P.S. Somethimesworking around in PSR IP is hard, it is better to delete the current module and bring another one to the design.