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alexsartin
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Registered: ‎11-19-2018

Processor System reset freezes PS with long aux_reset pulse

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In UltraScale+ I'm using a second Processor System Reset IP to reset only an AXI DMA peripheral and the AXI SmartConnect connect from the DMA(master) to PS(slave).

ext_reset_in is connect to PS/pl_resetn0 and aux_reset_in is controlled by an AXI GPIO.

When asserting aux_reset_in for a very short period (us) everything works fine but for longer periods (more than 1 second) everything freezes (all the FPGA logic including ILA inside and the ARM section as well).

 

Is that expected? The datasheet only specifies a minimum reset period not a max.

 

Regards,
Alex.

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dgisselq
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Registered: ‎05-21-2015

@alexsartin,

It really depends upon your bus topology and how you are generating your reset.  For example, if you are only resetting an AXI slave, then you might find a firewall useful.  If you are trying to reset a DMA--then you'll need to reset everything downstream to keep the design from hanging--not usually an easy thing to do.

Dan

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dgisselq
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Registered: ‎05-21-2015

@alexsartin,

How are you asserting this long reset?  From a button?  If so, then I'd look for 1) bouncing issues and 2) clock domain crossing issues on the reset line.

Dan

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alexsartin
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Registered: ‎11-19-2018
Hi Dan

The reset is done by software in the ARM side over AXI GPIO line.

We usually do a short pulse but we can't guarantee a software glitch freezing the reset asserted.
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dgisselq
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Registered: ‎05-21-2015

@alexsartin,

Then I'd look for something that is attempting to access those peripherals while the reset is active.  Such an access could easily hang the whole design.

Dan

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alexsartin
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Registered: ‎11-19-2018

It could be some sort of that. The DMA is in reset while the PS is trying to read something in the AXI interface.

When the DMA was in reset by the Processor System Reset IP no one was actively reading the DMA, but maybe the linux were reading other AXI slave devices. That XI was not in reset nor the other devices though.

Is there any safety measure I can do in the FPGA side to prevent the whole system glitch?

Regards,
Alex;

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dgisselq
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Registered: ‎05-21-2015

@alexsartin,

It really depends upon your bus topology and how you are generating your reset.  For example, if you are only resetting an AXI slave, then you might find a firewall useful.  If you are trying to reset a DMA--then you'll need to reset everything downstream to keep the design from hanging--not usually an easy thing to do.

Dan

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alexsartin
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Registered: ‎11-19-2018

Thank you  @dgisselq.

The links provided were very helpful.

I think that's exactly the problem: AXI DMA slave hanging a transaction and glitching the whole system. 

I made an internal logic to safely rest the Processor System Reset IP. In that case the DMA is reset by a shorter time than the AXI timeout avoiding the AXI hang. 

But I will try out using the AXI firewall as well.

 

Regards,
Alex.

 

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