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Contributor
Contributor
591 Views
Registered: ‎06-06-2017

Provide control signals to a logic design

Hi all

I have created a design (in VHDL) which purpose is to control the data from an ADC. This controller has the following inputs:

  • an Enable signal (std_logic) 
  • a Reset signal (std_logic)
  • a Command singal (std_logic vector (2 downto 0))
  • a NumofSamples (Unsigned (7downto 0))

My goal is to assign values to these signal from the PS with the application running under Linux. The frequency is once every 400ns.

Which is the best way to do it? Using AXI_GPIO? In a similar post https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/AXI-GPIO-too-slow/m-p/725431/highlight/true#M13994 it was was suggested that GPIO is not the right solution due to speed.

 

Thanks

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Teacher
Teacher
563 Views
Registered: ‎07-09-2009

Re: Provide control signals to a logic design

use the PL to make a AXI interface that talks to the adc,

 

then pass the answers back to the PL.

 

 

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Contributor
Contributor
541 Views
Registered: ‎06-06-2017

Re: Provide control signals to a logic design

Hi @drjohnsmith,

I didn't quite follow your suggestion. Do you mean to add an AXI-Lite interface to my design? Can you give an example?

 

Thanks in advance!!

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Teacher
Teacher
533 Views
Registered: ‎07-09-2009

Re: Provide control signals to a logic design

You have two choices with all these IO

 

You either toggle the pins from the PS side, 

  or you toggle pins from the PL side.

 

On the PS side, there are various peripherals that help the processor toggle pins,

    such as the SPI block, the UARTs et all.

 

If there is not a peripheral on the PS side that can interface for you

   you either need to 'bit bang; the IO pins on a PS GPIO,

       which is slow 

 

or you have a peripheral on the PL side 

 

this can be an off the shelf block, 

    like GPIO, I2C, SPI , UART 

 

or you write your own PL code,

 

 

 

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