Ps-PL interface. Finding a way to move large amount of data between PS-PL

[shantan1]

hi,
I want to send large amount of data between PS-PL (approximately 25KB) which is sent to PL logic. However, there is no master (BRAM, AXI etc.) in the PL logic. Is there a way to access BRAM or something directly in Verilog RTL in PL?

I want to index BRAM like this:
pl_config_reg = bram_reg[1023:0];

pl_config_reg2 = bram_reg[2047:1024];

[vanmierlo]

Your example does not look like anything streaming to me.

[shantan1]

K

[tedbooth]

@shantan1 

How about providing a higher level description of what you are trying to accomplish?  From there, we might be able to offer suggestions.

[shantan1]

As mentioned in my question description:

I want to send large amount of data between PS-PL (approximately 25KB) which is sent to PL logic. However, there is no master (BRAM, AXI etc.) in the PL logic.

Any solution is welcome. If you think the question is incorrect or unclear, please provide your best solution.
Thanks.

[olupj]

@shantan1,

I am pretty sure all PL-PS interfaces are AXI-MM. If you really have streaming data (some correctly question that statement) you can use "AXI Memory Mapped to Stream Mapper IP" that can interconnect AXI-MM and AXI-S interfaces.

Without more info, it's hard to help you.

-Jerry

[shantan1]

Sorry for my wrong use of jargon, I do not want streaming interface. I have updated my title.

The real problem is that there is no master in the PL. What solution do you recommend for AXI-MM if there is no master in the PL?

[vanmierlo]

I would not consider 25KB to be a large amount since it easily fits in a few (7) BRAM. Even the Z7007 has 50 BRAM. If you connect one side of 8 dual-ported BRAMs through an AXI BRAM controller to the AXI bus and use the other side as random access interface in your PL you could be quickly on your way. 

[shantan1]

Thanks @vanmierlo 

"Use the other side as random access interface in your PL"

What do you mean by this exactly? Please forgive me for my naivete, I am new to this domain.
How will the logic in my PL access the 25KB data? 
In my understanding, I have to constantly offload BRAM data in PL logic (wherever necessary) using a custom RTL module.

[olupj]

@shantan1 

There's Master and Slave AXI-MM interfaces between the PS-PL. Check the processing system IP configuration. So you can have a bus master (DMA controller is most likely) in the PL for this data transfer.

>>How will the logic in my PL access the 25KB data?
>>In my understanding, I have to constantly offload BRAM data in PL logic (wherever necessary) using a custom RTL module.

Use a DMAC core in the PL side (AXI Direct Memory Access being one candidate).

Develop your BRAM with an AXI-MM interface facing the DMAC, possibly use the AXI BRAM Controller IP, but I haven't use it before.

When your data transfer is ready signal (interrupt) the PS from the FPGA fabric (so sure you'll have to write some RTL - probably).

When the PS receives the interrupt, it sets up the DMA transaction and your data can be transferred from PL to PS.

Have fun,

Jerry

[u4223374]

@shantan1 If the real problem is that there is no master in the PL, why not just put a master in the PL? Problem solved! Xilinx provides a range of suitable blocks (eg. the AXI DMA) that can act as an AXI Master and pull data out of the PS.

[vanmierlo]

If you don't have and don't want an AXI master in your PL, my solution to use a BRAM controller still works. The BRAM controller is an AXI slave. The PS can access it at will.

With 'other side' I meant the other side of the dual-ported BRAM. One side must be connected to the BRAM controller, the other side is randomly accessible from your PL in the manner you described in your first post: pl_config_reg = bram_reg[1023:0];

If you really need to read 1024 bits at once though, you will have to use some more BRAMs as each only has 64 bits available.

But the real question is of course: what are you trying to achieve? To me it now looks like you want to send some static configuration data of 200 vectors of 1024 bit to the PL which you need to access randomly or sequentially, at high frequency, but not concurrently.

[dpaul24]

@shantan1 ,

I agree with the solution from @u4223374 .

Your AXI BRAM at the PL needs to store the data. Now AXI is a master-slave based design. So as I see it, to put data from the PS, the AXI Master at PS just needs to do a burst write to the AXI Slave BRAM at PL. Work done!

[vanmierlo]

@dpaul24 How can you agree with someone that says "put an AXI master in the PL" and then advise to use the AXI master inside the PS ?

[dpaul24]

@vanmierlo ,

advise to use the AXI master inside the PS ?

Apologies, I did not notice this.

Ah here....... "Xilinx provides a range of suitable blocks (eg. the AXI DMA) that can act as an AXI Master and pull data out of the PS."

I guess it is a typo from @u4223374 .

I assume the OP knows that if one side is master the side has to be slave. So if PS side is pushing data to PL and is having the master, the PL side would be the slave. This is very very basic stuff. It is better to have the AXI BRAM as a slave in the PL.

[vanmierlo]

---

@dpaul24 wrote:

Ah here....... "Xilinx provides a range of suitable blocks (eg. the AXI DMA) that can act as an AXI Master and pull data out of the PS."

I guess it is a typo from @u4223374 .

I don't think so. The mentioned AXI DMA *is* an AXI Master and thus must be connected to one of the slave ports of the PS (HP, ACP, GP). It can *pull* the data from DDR memory and provide it as a stream to the PL. But the OP does not want a stream.

[shantan1]

I know it has to be a slave. But, how will logic in PL access the data inside BRAM. There has to be an interface with din, dout, clk, rst etc. That was my problem, but it is now resolved. Thanks.

[shantan1 · Accepted solution]

Thank you everyone for the responses. I resolved the problem by finding an IP which converts AXI to "Custom-Interface" (undisclosable by NDA).

However, it is still unclear to me, how can logic in my PL use BRAM data?

Zynq PS -> AXI BRAM CTRL -> BRAM Memory -> ????? -> RTL logic (basic Verilog concurrent statements like "assign").

How can I use the BRAM data in "assign" statement?

Should it be "assign mybus = bram[31:0];" ?
I know BRAM requires an interface. But I do not want to implement an interface that constantly fetches data from BRAM and puts in different registers in RTL logic. 

Why doesn't Xilinx have a simple solution to send data from Zynq to gates? I do not have BRAM interface and do not want to make it.

The best I could do is Vivado's "Create AXI-Lite slave IP" and make all registers external so I can use them in "assign" statements in Verilog 

I know this is a basic question, but its better to ask stupid questions now as a T2 level Engineer than after I become a Senior Engineer or manager.
You are free to judge me

[vanmierlo]

You started by asking to use BRAM and now you state that you don't want BRAM but need registers instead.

Yes, registers are best attached to an AXI-Lite interface. Using Vivado's "Create AXI-Lite slave IP" is a good starting point.