02-26-2015 02:37 PM
I get this critical error when connecting the Quad SPI block to an AXI Interconnect with the QSPI performance mode enabled:
[BD 41-237] Bus Interface property MAX_BURST_LENGTH does not match between /cfg_spi/cfg_spi_primary/AXI_FULL(16) and /cfg_spi/cfg_spi_bus/m00_couplers/auto_ds/M_AXI(256)
Not sure how to fixe it.
07-21-2016 11:11 PM
[BD 41-237] Bus Interface property MAX_BURST_LENGTH does not match between /cfg_spi/cfg_spi_primary/AXI_FULL(16) and /cfg_spi/cfg_spi_bus/m00_couplers/auto_ds/M_AXI(25
Burst length in non XIP mode is fixed to 16 and XIP mode it is 256. Looks like you are using non XIP mode hence the warning by the tool which is valid.
09-11-2017 06:35 AM
I have the same problem but I don't understand your answer.
I don't want to use the XIP mode (my SPI interface is not used for a ROM) but I need burst transfers, so I enabled performance mode (16 is enough though). I used the SmartConnect IP in my case but I get the exact same error as for the AXI Interconnect mentionned above.
Why do I get this error ? It seems that the M_AXI port of SmartConnect IP is not able to adapt its burst length to that of the QSPI IP. So I assume it's not a setting problem and the error comes from a bug in SmartConnect (as it is supposed to adapt to the slave automatically). Am I wrong ? What should I do to correct this problem ? Am I forced to use the XIP mode !?
09-12-2017 04:20 AM - edited 09-12-2017 04:22 AM
I had 2 levels of AXI interconnections using SmartConnect. The first one had 4 slaves that go into 4 subblocks (I created hierarchy cells) each with one SmartConnect IP with 8 slaves, for a total of 32 QuadSPI IPs. I removed the first stage and replaced it by 4 external AXI ports (with burst length set to 16) to see if it would work better but it didn't. Then I tried to replace the SmartConnect IPs inside each subblocks by AXI interconnect IPs and it did work.
So in my case at least the problem seems related to the SmartConnect IP.
I wonder if the hierarchy prevents the SmartConnect IP from setting properly.
Do you have any idea about this ?
11-13-2017 04:35 AM - edited 11-13-2017 04:46 AM
It's both Zync (not Microblaze) and a home-made DMA master, one for each SPI.
PS: I gave up using SmartConnect and I came back to the AXI Interconnect IP. The SmartConnect IP is about 5-8 times bigger (I dont remember exactly) in terms of ressources used (at least after synth) and doesn't give any option (AND doesn't work).