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malstew
Visitor
Visitor
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Registered: ‎06-05-2020

QUAD SPI not seen in schematic/device view

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Hello, 

we have included the QUAD SPI in our design (on Kintex Ultrascale kcku5p) but when we run implementation and look at the schematic or the "Device" view we can't see the output ports.  The QUAD SPI is configured as:

"Flash(Memory) access through STARTUP primitive --> Use STARTUP Primitive INTERNAL to IP.  

In fact, I can't see any of the BANK 0 ports when I look at the DEVICE view (the view that show where on the DIE the IO/logic can be found).  If I export the IO I see nothing to indicate that the "dedicated" IO ports for the QUAD SPI are being used.  

QUestion: 1) How do I get the Bank0 ports that are being used to show up in the IO report? 

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katsuki
Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎11-05-2019

Hi @malstew 

If you want to know the allocation of dedicated pin of BANK0, you can refer to UG575.

UG575 UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification

In your AXI QSPI IP Config, the external ports CCLK, CS, D of the AXI QSPI IP are connected to dedicated pins via the STARTUP primitive.

If you want to access Config QSPI memory using AXI QSPI IP, the following XAPP will be helpful.

XAPP1280 UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 Application Note

Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.

 

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katsuki
Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎11-05-2019

Hi @malstew 

If you want to know the allocation of dedicated pin of BANK0, you can refer to UG575.

UG575 UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification

In your AXI QSPI IP Config, the external ports CCLK, CS, D of the AXI QSPI IP are connected to dedicated pins via the STARTUP primitive.

If you want to access Config QSPI memory using AXI QSPI IP, the following XAPP will be helpful.

XAPP1280 UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 Application Note

Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.

 

View solution in original post

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katsuki
Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Hi @malstew 

If you understand or already issue has resolved, Kudo, and Accept as Solution.
If you have any questions, you can post them.

Thank you.

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