I'm planning to write custom IP that will have to contend for the DDR interface on a Zynq-7000, and was hoping to use the AXI QoS interface to manage the timing relationships to the rest of the system. The IP is primarily based around a FIFO, and I want to issue read requests with greater urgency as the FIFO gets nearer to empty.
This would be easy to base around the AXI DataMover, except that the DataMover doesn't support the 4-bit QoS signals. It supports a 4-bit USER though, which I've got no use for. Is there any reason I couldn't cross over the outputs and poach the USER bits to drive QoS?