01-05-2015 06:26 AM
I have ordered Zynq-7000 Video and Imaging Kit needs clarification on the following points:
1- plz. tell the IP cores avalable from xilinx Video & imaging IP pack are in C,VHDL OR verilog.
2- Can the IP cores be ported on FPGA fabric or processing system or can be both.
3- if user needs a custom implemenattion of some video codec using OPEN CV libraries can it be ported on both Fabric and processing system or both.
4- whther the refrence design provided stores the video frame in DDR3, as no video encoder has been used in the design flow seen.
looking for ur kind reply.
01-05-2015 09:10 AM
1. These are the IPs in the Video and Image Processing pack: http://www.xilinx.com/products/intellectual-property/ef-di-vid-img-ip-pack.html. You can instantiate them in either VHDL or Verilog designs.
2. These particular IP are fabric-only.
3. Yes, the ARM will run standard OpenCV libs and Vivado HLS also supports OpenCV so it should be very easy to port.
4. I don't understand your question. Are you looking for an example design showing video encoder?
01-05-2015 08:53 PM
thanks for ur reply....
1- plz clarify me : Can OpenCV libraries be executed/imlemented on FPGA fabric also.If yes HOW?
2- Does Vivado HLS provide OpenCV libraries.Plz. help me to track the path for the same.
3- do we have any small refrence design to understand/test OpenCV intergration with tool.
4- Do the OpenCV libraries provide video encoder API also.Can we locate them.
Looking for ur great help.
01-06-2015 08:05 AM
Here's some documentation to get you going: