07-25-2019 02:24 AM - edited 07-25-2019 02:26 AM
here is my problem:
I want to use store and forward mode using the AXI stream fifo, and I need the output stream to be 64 bit wide
* I configured the AXI stream for store and forward mode
* I chose AXI4 full as data interface (to make the output 64 bit)
at this point the are 2 slave interfaces exposed: AXI4 lite and AXI4 lite. as I understad from the block diagram the internal fifos are both connected to both AXI4 and AXI4 lite interface, and the AXI4 lite is also used to access the register space.
my first question is: can I use full AXI as data path, and write my 32bit data using the AXI4 lite slave interface or I have to write data using the AXI 4 full interface if i select AXI4 full as data path
* I tried programming the fifo, I follow the guidelines in the data sheet, after writing the data and then writing the transmit length register, nothing happens.
anyone got this working and get shed some light?
07-25-2019 07:46 AM
Judging from a quick read of the manual, you should be able to use either AXI-lite or AXI for the data path, although I'm not sure how the core will handle misalignment when you write a 32-bit word to the AXI-lite interface even though the FIFO uses a 64-bit interface.
To your second question, you may need to set the TLAST AXI-stream parameter to indicate that a whole packet has been received before being able to read from the stream.
07-26-2019 01:14 AM
issue solved, however now I have a second problem..
using the full axi port on this fifo, i must write 64 bit data , and since i connect to it from BAR_0 which is an axi lite master port, i can only write 32b data.
07-26-2019 05:51 AM
For your new questions please post another post detialing the issue with more details.