09-18-2017 02:21 AM
We are using Zynq xc7z020clg484-1 in a custom board. The Gigabit Ethernet controller of Zynq is used in our project and is assigned to the MIO pins with RGMII interface. The MIO banks are supplied with 3.3V. The incompatibility of the RGMII interface on Zynq PS with LVCMOS33 is discovered lately. But the ethernet PHY chip used on board supports 3.3V for the RGMII interface. Now that the board fabrication and assembly is completed, can we use the RGMII interface on zynq with LVCMOS33 ignoring the warnings or is their any workaround.
10-03-2017 07:19 PM
The operational voltage of the PS-MIO RGMII is dictated by the voltage applied to Bank 1. I assumed all of your MIO interfaces in Bank 1 are running at the same voltage: 3.3V. Since you've already fabricated your board, your choices are limited. You can certainly try the RGMII interface at 3.3V, since your PHY accommodates that voltage.
The Zynq datasheet guarantees operation at 2.5V--the voltage RGMII is specified for. I don't think they guarantee it won't work at 3.3V. (Vivado 17.2 will generate this design; I don't have hardware to check it, though.) The datasheet timing for the MIO RGMII is pretty good. You'll lose some margin, but there's a solid chance it will work at nominal temperature and voltage--assuming your interface was routed to spec. A re-spin of your custom PCB would be recommended, if you need guaranteed operation in the long run.
Please reply and let us know how it goes.
10-04-2017 08:30 PM
For what it's worth, Enclustra uses 3.3V RGMII on their Mercury SoMs. The user manual notes that this is not officially supported but that their testing suggests it's fine. We've never had any trouble with it (we use their ZX1 SoM) although our use of the ethernet port has been fairly limited.
As @jg_bds has said, for guaranteed reliable operation you should respin the board - but right now I'd just ignore the warning.
10-04-2017 10:36 PM
To adhere to the RGMII specification we have reduced the IO voltage for the MIO bank to 2.7V and are using the LVCMOS25 IO standards from Vivado for the Gigabit Ethernet controller ports. But we are unable to detect the PHY connected using the MDIO interface. Also the MDC-MDIO interface is being shared with two PHYs on the board. What can be the reason behind PHY not being detected.
10-05-2017 04:35 AM
I'm unsure as to what you're saying: can you detect 1 of the 2 PHYs, but not the other? Or can you detect no PHYs?
Either way, confirm:
1) the PHY you're trying to access is out of reset, and it has received a proper reset
2) the PHY's MDIO address setting, and make sure that's the address you're trying to access it at
3) the clock source for the PHY (free-running/oscillator/crystal) is active and at the correct frequency
4) the pull-up on the MDIO data line is present and appropriate
5) the MDIO clock at the PHY looks correct
A lot of people mistakenly route the MDIO clock in daisy-chain fashion to multiple PHYs. (It really should be buffered if it's sent to multiple destinations.) The PHY at the end of the chain is happy, because he gets a proper edge--but other the PHY(s) in the chain could end up with a glitch on the clock edge, and their MDIO interface becomes unreliable.
Lastly, monitor the MDIO clock and data lines during an access, to make sure they're moving. If they're not moving, the MDIO configuration within the Zynq might not be correct.
12-19-2017 06:28 AM
We were successful in bringing up the RGMII interfaces with MIO banks supplied with 2.96V and the IO standards being set to LVCMOS25. But the RGMII interface 2 is working only at 10/ 100 Mbps while the RGMII interface 1 is working as expected at 10/ 100/ 1000 Mbps. The RGMII interface 2 is giving auto negotiation error at 1000Mbps. We are planning to test the functionality with MIO banks supplied with 3.3V. What is the recommended IO standard at this voltage - LVCMOS25 or LVCMOS33.
03-20-2019 10:17 PM
We did the same thing, a custom board with PS MIO Ethernet connection to BANK1 and it is driven with 3v3. Did you find any chance to try your suggestion of 3v3 supplied bank volts ethernet usage LVCMOS25 or LVCMOS33?
10-14-2019 07:29 PM
I have encountered the same problem. Have you verified this scheme, does “RGMII interface with LVCMOS33 IO standard on Zynq” affect the performance of RGMII? For example, network transmission rate and so on.