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amir.massah
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Registered: ‎10-12-2018

Random AXI Read Transaction

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Hi to all,

I have an AXI master IP which is supposed to read data from DDR4 in PS part of a Zynq US+ device. I am using Xilinx AXI VIP for verifying my IP. Once a burst is started, the RVALID signal is high through the whole burst. However, I want to verify my IP under different random conditions which means RVALID signals should be low for some of the beats. How can I do that?

I have already asked this question in this forum but I did not get any reply:

https://forums.xilinx.com/t5/Simulation-and-Verification/RVALID-signal-generation/m-p/920838#M24537 

I would be really grateful if anybody could help me or give me a hint.

Thank you very much in advance. 

Regards,

Amir 

 

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amir.massah
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Registered: ‎10-12-2018

Hi,

I found the solution, and I am writing here for others.

Actually, my question was a little unclear. It was about the memory model in AXI slave. This IP provides a different API function set to configure the delay between the beats of a read burst. There are actually two policies for setting the delay gap between beats which are XIL_AXI_MEMORY_DELAY_FIXED and XIL_AXI_MEMORY_DELAY_RANDOM and the corresponding function to set is set_inter_beat_gap_delay_policy. The default setting is the random case with the minimum and maximum value of 0, which means there is no delay between two betas and the RVALID signal is high through a burst. In order to change the min/max value of the delay, a function named set_inter_beat_gap_range should be used. Also, if a fixed delay gap policy is the desired one, set_inter_beat_gap API function is used to select the delay value.  

Regards,

Amir

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markcurry
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Registered: ‎09-16-2009

Amir,

I'm not familiar with using the Xilinx VIP for AXI - we have our own BFM models for AXI - written in SystemVerilog.  So, I'm not sure how much this will help you or not, but I'll explain anyway in hopes that you'll find it useful.

What you're trying to do is a common verification technique, and I'd hope the Xilinx VIP would offer it somehow.

How we do it in systemverilog is to utilize the randcase functions:

randcase
   1 : ready = 1;
   9 : ready = 0;
endcase

In this (simplified) case - we constrain ready to be high with a weight of 1, and low with a weight of 9.  So, 1/10 time the BFM is ready, 9/10 it's not.

When we are driving AXI busses with the testbench, this code is usually within a SystemVerilog interface.  We have tasks() setup to drive the RREADY, and other lines.  The weights are not normally hardcoded as I've shown in this example, but usually arguments passed to the task (with suitable defaults).  Be careful to properly allow for always READY, and/or never READY corner cases.

As I said, any VIP should allow hooks for these types of things (perhaps implemented in a different way), but I've not used the Xilinx AXI VIP, so can't comment on that use case.

Regards,

Mark

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amir.massah
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Registered: ‎10-12-2018

Hi @markcurry,

Thank you very much for your reply and useful information.

Actually, AXI VIP provides some classes and API functions for setting and configuration. For example, in order to generate a ready signal, it has a class named axi_ready_gen that offers different patterns for the ready signal. 

My problem, actually, is providing a situation for different patterns of the RVALID signal. In other words, I want my slave AXI VIP to put the RVALID signal low sometimes. 

Regards,

Amir

 

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amir.massah
Adventurer
Adventurer
1,314 Views
Registered: ‎10-12-2018

Hi,

I found the solution, and I am writing here for others.

Actually, my question was a little unclear. It was about the memory model in AXI slave. This IP provides a different API function set to configure the delay between the beats of a read burst. There are actually two policies for setting the delay gap between beats which are XIL_AXI_MEMORY_DELAY_FIXED and XIL_AXI_MEMORY_DELAY_RANDOM and the corresponding function to set is set_inter_beat_gap_delay_policy. The default setting is the random case with the minimum and maximum value of 0, which means there is no delay between two betas and the RVALID signal is high through a burst. In order to change the min/max value of the delay, a function named set_inter_beat_gap_range should be used. Also, if a fixed delay gap policy is the desired one, set_inter_beat_gap API function is used to select the delay value.  

Regards,

Amir

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