Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers
To reframe the question. In the section titled: "SPI Master and Slave Devices where Registers/FIFOs are Filled Before the SPI Transfer Begins and Multiple Discrete 8-bit Transfers are Performed (Optional Mode)"
Does "Discrete 8-bit transfers" mean that chip select will toggle every 8 bits?
Like in a spidev example, you'd be able to maybe setup your struct to have a time delay on each toggle using the delay_us parameter. ex)
I can't speak to the code snippet, but the documentation section you reference describes a scenario where a single 8-bit transfer is performed in a single transaction. A transaction is defined as what happens (inclusively) between a SPI chip select asserting, and that chip select de-asserting.