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cchamp
Participant
Participant
7,090 Views
Registered: ‎07-11-2011

Read 128 bits FIFO with microblaze

Hello,

 

I have connected my own IP to microblaze through a 128 bits read FIFO. In CIP I enabled packet mode, burst and interrupt. Interrupt are working fine but when I  try to read data  with microblaze which has 32 bits registers, I only get the 32 msb. How can I access  others ? Is there any parameter to modify  when implementing my peripheral or data are in some others registers in microblaze and how can I read them ?

 

Thanks for help

 CC

 

EDK 14.4

virtex5 lx

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9 Replies
golson
Scholar
Scholar
7,068 Views
Registered: ‎04-07-2008

I pretty sure that your FIFO is a 32 bit interface to the microblaze.  If you are reading the FIFO make sure you are reading

at the correct offset address also. 

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cchamp
Participant
Participant
7,063 Views
Registered: ‎07-11-2011

I think I'm reading at the correct offset address.

In SDK when I check data in memory, it looks fine, all my 128 bits data are written there. I just can't find how to read them in microblaze. When reading I get the 32 msb and if I try to read the next 32 bits in memory I get the same 32 msb

Thanks for your help

 

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golson
Scholar
Scholar
7,060 Views
Registered: ‎04-07-2008

Check to see the value of vacancy or occupancy in the fifo.  Make sure you have data in it before starting to read it.

 

Every time you read it the fifo should output a new 32 bit word.  But if there is no data in the fifo it will hold the value

that was being output previously.  if there is no data in the fifo and you read it the ptr will stay pointing at the same place

and the output data will not change.

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cchamp
Participant
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Registered: ‎07-11-2011

Reading FIFO is triggered by an interrupt on almost full flag of FIFO, so there must be data in FIFO. When I check memory, there are data. I think it's 2 different problems

Reading a 128 bits FIFO with microblaze and having the same 32 bits word each time reading

When I read a 32 bit FIFO, it works fine

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golson
Scholar
Scholar
7,044 Views
Registered: ‎04-07-2008

Hi,

  Could you post the top level IPIF file here.  I would like to see the design you are talking about and see

if it is different to designs I have done.

 

Thanks

 

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cchamp
Participant
Participant
7,038 Views
Registered: ‎07-11-2011

Hi,

 

Here is my top level IPIF file

 

------------------------------------------------------------------------------
-- cpt_test.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          cpt_test.vhd
-- Version:           2.01.a
-- Description:       Top level design, instantiates library components and user logic.
-- Date:              Fri Mar 22 10:15:03 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;

library interrupt_control_v2_01_a;
use interrupt_control_v2_01_a.interrupt_control;

library rdpfifo_v4_02_a;
use rdpfifo_v4_02_a.rdpfifo_top;

library plbv46_slave_burst_v1_01_a;
use plbv46_slave_burst_v1_01_a.plbv46_slave_burst;

library cpt_test_v2_01_a;
use cpt_test_v2_01_a.user_logic;

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_BASEADDR                   -- PLBv46 slave: base address
--   C_HIGHADDR                   -- PLBv46 slave: high address
--   C_SPLB_AWIDTH                -- PLBv46 slave: address bus width
--   C_SPLB_DWIDTH                -- PLBv46 slave: data bus width
--   C_SPLB_NUM_MASTERS           -- PLBv46 slave: Number of masters
--   C_SPLB_MID_WIDTH             -- PLBv46 slave: master ID bus width
--   C_SPLB_NATIVE_DWIDTH         -- PLBv46 slave: internal native data bus width
--   C_SPLB_P2P                   -- PLBv46 slave: point to point interconnect scheme
--   C_SPLB_SUPPORT_BURSTS        -- PLBv46 slave: support bursts
--   C_SPLB_SMALLEST_MASTER       -- PLBv46 slave: width of the smallest master
--   C_SPLB_CLK_PERIOD_PS         -- PLBv46 slave: bus clock in picoseconds
--   C_INCLUDE_DPHASE_TIMER       -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
--   C_FAMILY                     -- Xilinx FPGA family
--
-- Definition of Ports:
--   SPLB_Clk                     -- PLB main bus clock
--   SPLB_Rst                     -- PLB main bus reset
--   PLB_ABus                     -- PLB address bus
--   PLB_UABus                    -- PLB upper address bus
--   PLB_PAValid                  -- PLB primary address valid indicator
--   PLB_SAValid                  -- PLB secondary address valid indicator
--   PLB_rdPrim                   -- PLB secondary to primary read request indicator
--   PLB_wrPrim                   -- PLB secondary to primary write request indicator
--   PLB_masterID                 -- PLB current master identifier
--   PLB_abort                    -- PLB abort request indicator
--   PLB_busLock                  -- PLB bus lock
--   PLB_RNW                      -- PLB read/not write
--   PLB_BE                       -- PLB byte enables
--   PLB_MSize                    -- PLB master data bus size
--   PLB_size                     -- PLB transfer size
--   PLB_type                     -- PLB transfer type
--   PLB_lockErr                  -- PLB lock error indicator
--   PLB_wrDBus                   -- PLB write data bus
--   PLB_wrBurst                  -- PLB burst write transfer indicator
--   PLB_rdBurst                  -- PLB burst read transfer indicator
--   PLB_wrPendReq                -- PLB write pending bus request indicator
--   PLB_rdPendReq                -- PLB read pending bus request indicator
--   PLB_wrPendPri                -- PLB write pending request priority
--   PLB_rdPendPri                -- PLB read pending request priority
--   PLB_reqPri                   -- PLB current request priority
--   PLB_TAttribute               -- PLB transfer attribute
--   Sl_addrAck                   -- Slave address acknowledge
--   Sl_SSize                     -- Slave data bus size
--   Sl_wait                      -- Slave wait indicator
--   Sl_rearbitrate               -- Slave re-arbitrate bus indicator
--   Sl_wrDAck                    -- Slave write data acknowledge
--   Sl_wrComp                    -- Slave write transfer complete indicator
--   Sl_wrBTerm                   -- Slave terminate write burst transfer
--   Sl_rdDBus                    -- Slave read data bus
--   Sl_rdWdAddr                  -- Slave read word address
--   Sl_rdDAck                    -- Slave read data acknowledge
--   Sl_rdComp                    -- Slave read transfer complete indicator
--   Sl_rdBTerm                   -- Slave terminate read burst transfer
--   Sl_MBusy                     -- Slave busy indicator
--   Sl_MWrErr                    -- Slave write error indicator
--   Sl_MRdErr                    -- Slave read error indicator
--   Sl_MIRQ                      -- Slave interrupt indicator
--   IP2INTC_Irpt                 -- Interrupt output to processor
------------------------------------------------------------------------------

entity cpt_test is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
    C_HIGHADDR                     : std_logic_vector     := X"00000000";
    C_SPLB_AWIDTH                  : integer              := 32;
    C_SPLB_DWIDTH                  : integer              := 128;
    C_SPLB_NUM_MASTERS             : integer              := 8;
    C_SPLB_MID_WIDTH               : integer              := 3;
    C_SPLB_NATIVE_DWIDTH           : integer              := 128;
    C_SPLB_P2P                     : integer              := 0;
    C_SPLB_SUPPORT_BURSTS          : integer              := 1;
    C_SPLB_SMALLEST_MASTER         : integer              := 32;
    C_SPLB_CLK_PERIOD_PS           : integer              := 10000;
    C_INCLUDE_DPHASE_TIMER         : integer              := 1;
    C_FAMILY                       : string               := "virtex5"
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
      clk : IN std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    SPLB_Clk                       : in  std_logic;
    SPLB_Rst                       : in  std_logic;
    PLB_ABus                       : in  std_logic_vector(0 to 31);
    PLB_UABus                      : in  std_logic_vector(0 to 31);
    PLB_PAValid                    : in  std_logic;
    PLB_SAValid                    : in  std_logic;
    PLB_rdPrim                     : in  std_logic;
    PLB_wrPrim                     : in  std_logic;
    PLB_masterID                   : in  std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
    PLB_abort                      : in  std_logic;
    PLB_busLock                    : in  std_logic;
    PLB_RNW                        : in  std_logic;
    PLB_BE                         : in  std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
    PLB_MSize                      : in  std_logic_vector(0 to 1);
    PLB_size                       : in  std_logic_vector(0 to 3);
    PLB_type                       : in  std_logic_vector(0 to 2);
    PLB_lockErr                    : in  std_logic;
    PLB_wrDBus                     : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);
    PLB_wrBurst                    : in  std_logic;
    PLB_rdBurst                    : in  std_logic;
    PLB_wrPendReq                  : in  std_logic;
    PLB_rdPendReq                  : in  std_logic;
    PLB_wrPendPri                  : in  std_logic_vector(0 to 1);
    PLB_rdPendPri                  : in  std_logic_vector(0 to 1);
    PLB_reqPri                     : in  std_logic_vector(0 to 1);
    PLB_TAttribute                 : in  std_logic_vector(0 to 15);
    Sl_addrAck                     : out std_logic;
    Sl_SSize                       : out std_logic_vector(0 to 1);
    Sl_wait                        : out std_logic;
    Sl_rearbitrate                 : out std_logic;
    Sl_wrDAck                      : out std_logic;
    Sl_wrComp                      : out std_logic;
    Sl_wrBTerm                     : out std_logic;
    Sl_rdDBus                      : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
    Sl_rdWdAddr                    : out std_logic_vector(0 to 3);
    Sl_rdDAck                      : out std_logic;
    Sl_rdComp                      : out std_logic;
    Sl_rdBTerm                     : out std_logic;
    Sl_MBusy                       : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    Sl_MWrErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    Sl_MRdErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    Sl_MIRQ                        : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    IP2INTC_Irpt                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute MAX_FANOUT : string;
  attribute SIGIS : string;

  attribute SIGIS of SPLB_Clk      : signal is "CLK";
  attribute SIGIS of SPLB_Rst      : signal is "RST";
  attribute SIGIS of IP2INTC_Irpt  : signal is "INTR_LEVEL_HIGH";

end entity cpt_test;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of cpt_test is

  ------------------------------------------
  -- Array of base/high address pairs for each address range
  ------------------------------------------
  constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 31) := (others => '0');
  constant USER_SLV_BASEADDR              : std_logic_vector     := C_BASEADDR or X"00000000";
  constant USER_SLV_HIGHADDR              : std_logic_vector     := C_BASEADDR or X"000000FF";
  constant INTR_BASEADDR                  : std_logic_vector     := C_BASEADDR or X"00000100";
  constant INTR_HIGHADDR                  : std_logic_vector     := C_BASEADDR or X"000001FF";
  constant RFF_REG_BASEADDR               : std_logic_vector     := C_BASEADDR or X"00000200";
  constant RFF_REG_HIGHADDR               : std_logic_vector     := C_BASEADDR or X"000002FF";
  constant RFF_DAT_BASEADDR               : std_logic_vector     := C_BASEADDR or X"00000300";
  constant RFF_DAT_HIGHADDR               : std_logic_vector     := C_BASEADDR or X"000003FF";

  constant IPIF_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE     :=
    (
      ZERO_ADDR_PAD & USER_SLV_BASEADDR,  -- user logic slave space base address
      ZERO_ADDR_PAD & USER_SLV_HIGHADDR,  -- user logic slave space high address
      ZERO_ADDR_PAD & INTR_BASEADDR,      -- interrupt control space base address
      ZERO_ADDR_PAD & INTR_HIGHADDR,      -- interrupt control space high address
      ZERO_ADDR_PAD & RFF_REG_BASEADDR,   -- read pfifo register space base address
      ZERO_ADDR_PAD & RFF_REG_HIGHADDR,   -- read pfifo register space high address
      ZERO_ADDR_PAD & RFF_DAT_BASEADDR,   -- read pfifo data space base address
      ZERO_ADDR_PAD & RFF_DAT_HIGHADDR    -- read pfifo data space high address
    );

  ------------------------------------------
  -- Array of desired number of chip enables for each address range
  ------------------------------------------
  constant USER_SLV_NUM_REG               : integer              := 1;
  constant USER_NUM_REG                   : integer              := USER_SLV_NUM_REG;
  constant INTR_NUM_CE                    : integer              := 4;
  constant RFF_NUM_REG_CE                 : integer              := 1;
  constant RFF_NUM_DAT_CE                 : integer              := 1;

  constant IPIF_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE   :=
    (
      0  => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
      1  => INTR_NUM_CE,                  -- number of ce for interrupt control space
      2  => RFF_NUM_REG_CE,               -- number of ce for read pfifo register space
      3  => RFF_NUM_DAT_CE                -- number of ce for read pfifo data space
    );

  ------------------------------------------
  -- Cache line addressing mode (for cacheline read operations)
  -- 0 = target word first on reads
  -- 1 = line word first on reads
  ------------------------------------------
  constant IPIF_CACHLINE_ADDR_MODE        : integer              := 0;

  ------------------------------------------
  -- Number of storage locations for the write buffer
  -- Valid depths are 0, 16, 32, or 64
  -- 0 = no write buffer implemented
  ------------------------------------------
  constant IPIF_WR_BUFFER_DEPTH           : integer              := 16;

  ------------------------------------------
  -- The type out of the Bus2IP_BurstLength signal
  -- 0 = length is in actual byte number
  -- 1 = length is in data beats - 1
  ------------------------------------------
  constant IPIF_BURSTLENGTH_TYPE          : integer              := 0;

  ------------------------------------------
  -- Width of the slave data bus (32, 64, or 128)
  ------------------------------------------
  constant USER_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;

  constant IPIF_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;

  ------------------------------------------
  -- Number of device level interrupts
  ------------------------------------------
  constant INTR_NUM_IPIF_IRPT_SRC         : integer              := 4;

  ------------------------------------------
  -- Capture mode for each IP interrupt (generated by user logic)
  -- 1 = pass through (non-inverting)
  -- 2 = pass through (inverting)
  -- 3 = registered level (non-inverting)
  -- 4 = registered level (inverting)
  -- 5 = positive edge detect
  -- 6 = negative edge detect
  ------------------------------------------
  constant USER_NUM_INTR                  : integer              := 1;
  constant USER_INTR_CAPTURE_MODE         : integer              := 5;

  constant INTR_IP_INTR_MODE_ARRAY        : INTEGER_ARRAY_TYPE   :=
    (
      0  => USER_INTR_CAPTURE_MODE
    );

  ------------------------------------------
  -- Device priority encoder feature inclusion/omission
  -- true  = include priority encoder
  -- false = omit priority encoder
  ------------------------------------------
  constant INTR_INCLUDE_DEV_PENCODER      : boolean              := true;

  ------------------------------------------
  -- Device ISC feature inclusion/omission
  -- true  = include device ISC
  -- false = omit device ISC
  ------------------------------------------
  constant INTR_INCLUDE_DEV_ISC           : boolean              := true;

  ------------------------------------------
  -- Read FIFO desired depth specified as a Log2(x) value (2 to 14)
  ------------------------------------------
  constant USER_RDFIFO_DEPTH              : integer              := 512;

  constant RFF_FIFO_DEPTH_LOG2X           : integer              := log2(USER_RDFIFO_DEPTH);

  ------------------------------------------
  -- Read FIFO packet mode feature inclusion/omision
  -- true  = include packet mode features
  -- false = omit packet mode features
  ------------------------------------------
  constant RFF_INCLUDE_PACKET_MODE        : boolean              := true;

  ------------------------------------------
  -- Read FIFO vacancy calculation inclusion/omision
  -- true  = include vacancy calculation
  -- false = omit vacancy calculation
  ------------------------------------------
  constant RFF_INCLUDE_VACANCY            : boolean              := true;

  ------------------------------------------
  -- Read FIFO enable for host bus data burst support
  -- true  = support host bus data bursting
  -- false = do not support host bus data bursting
  ------------------------------------------
  constant RFF_SUPPORT_BURST              : boolean              := (C_SPLB_SUPPORT_BURSTS /= 0);

  ------------------------------------------
  -- Index for CS/CE
  ------------------------------------------
  constant USER_SLV_CS_INDEX              : integer              := 0;
  constant USER_SLV_CE_INDEX              : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
  constant INTR_CS_INDEX                  : integer              := 1;
  constant INTR_CE_INDEX                  : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
  constant RFF_REG_CS_INDEX               : integer              := 2;
  constant RFF_REG_CE_INDEX               : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RFF_REG_CS_INDEX);
  constant RFF_DAT_CS_INDEX               : integer              := 3;
  constant RFF_DAT_CE_INDEX               : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RFF_DAT_CS_INDEX);

  constant USER_CE_INDEX                  : integer              := USER_SLV_CE_INDEX;

  ------------------------------------------
  -- IP Interconnect (IPIC) signal declarations
  ------------------------------------------
  signal ipif_Bus2IP_Clk                : std_logic;
  signal ipif_Bus2IP_Reset              : std_logic;
  signal ipif_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
  signal ipif_IP2Bus_WrAck              : std_logic;
  signal ipif_IP2Bus_RdAck              : std_logic;
  signal ipif_IP2Bus_AddrAck            : std_logic;
  signal ipif_IP2Bus_Error              : std_logic;
  signal ipif_Bus2IP_Addr               : std_logic_vector(0 to C_SPLB_AWIDTH-1);
  signal ipif_Bus2IP_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
  signal ipif_Bus2IP_RNW                : std_logic;
  signal ipif_Bus2IP_BE                 : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
  signal ipif_Bus2IP_Burst              : std_logic;
  signal ipif_Bus2IP_BurstLength        : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
  signal ipif_Bus2IP_WrReq              : std_logic;
  signal ipif_Bus2IP_RdReq              : std_logic;
  signal ipif_Bus2IP_CS                 : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
  signal ipif_Bus2IP_RdCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
  signal ipif_Bus2IP_WrCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
  signal intr_IPIF_Reg_Interrupts       : std_logic_vector(0 to 1);
  signal intr_IPIF_Lvl_Interrupts       : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
  signal intr_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
  signal intr_IP2Bus_WrAck              : std_logic;
  signal intr_IP2Bus_RdAck              : std_logic;
  signal intr_IP2Bus_Error              : std_logic;
  signal rff_RFIFO2IP_WrAck             : std_logic;
  signal rff_RFIFO2IP_AlmostFull        : std_logic;
  signal rff_RFIFO2IP_Full              : std_logic;
  signal rff_RFIFO2IP_Vacancy           : std_logic_vector(0 to RFF_FIFO_DEPTH_LOG2X);
  signal rff_FIFO2IRPT_DeadLock         : std_logic;
  signal rff_IP2Bus_Data                : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
  signal rff_IP2Bus_WrAck               : std_logic;
  signal rff_IP2Bus_RdAck               : std_logic;
  signal rff_IP2Bus_Error               : std_logic;
  signal user_Bus2IP_RdCE               : std_logic_vector(0 to USER_NUM_REG-1);
  signal user_Bus2IP_WrCE               : std_logic_vector(0 to USER_NUM_REG-1);
  signal user_Bus2IP_BurstLength        : std_logic_vector(0 to 8)   := (others => '0');
  signal user_IP2Bus_AddrAck            : std_logic;
  signal user_IP2Bus_Data               : std_logic_vector(0 to USER_SLV_DWIDTH-1);
  signal user_IP2Bus_RdAck              : std_logic;
  signal user_IP2Bus_WrAck              : std_logic;
  signal user_IP2Bus_Error              : std_logic;
  signal user_IP2Bus_IntrEvent          : std_logic_vector(0 to USER_NUM_INTR-1);
  signal user_IP2RFIFO_WrReq            : std_logic;
  signal user_IP2RFIFO_Data             : std_logic_vector(0 to USER_SLV_DWIDTH-1);
  signal user_IP2RFIFO_WrMark           : std_logic;
  signal user_IP2RFIFO_WrRelease        : std_logic;
  signal user_IP2RFIFO_WrRestore        : std_logic;

begin

  ------------------------------------------
  -- instantiate plbv46_slave_burst
  ------------------------------------------
  PLBV46_SLAVE_BURST_I : entity plbv46_slave_burst_v1_01_a.plbv46_slave_burst
    generic map
    (
      C_ARD_ADDR_RANGE_ARRAY         => IPIF_ARD_ADDR_RANGE_ARRAY,
      C_ARD_NUM_CE_ARRAY             => IPIF_ARD_NUM_CE_ARRAY,
      C_SPLB_P2P                     => C_SPLB_P2P,
      C_CACHLINE_ADDR_MODE           => IPIF_CACHLINE_ADDR_MODE,
      C_WR_BUFFER_DEPTH              => IPIF_WR_BUFFER_DEPTH,
      C_BURSTLENGTH_TYPE             => IPIF_BURSTLENGTH_TYPE,
      C_SPLB_MID_WIDTH               => C_SPLB_MID_WIDTH,
      C_SPLB_NUM_MASTERS             => C_SPLB_NUM_MASTERS,
      C_SPLB_SMALLEST_MASTER         => C_SPLB_SMALLEST_MASTER,
      C_SPLB_AWIDTH                  => C_SPLB_AWIDTH,
      C_SPLB_DWIDTH                  => C_SPLB_DWIDTH,
      C_SIPIF_DWIDTH                 => IPIF_SLV_DWIDTH,
      C_INCLUDE_DPHASE_TIMER         => C_INCLUDE_DPHASE_TIMER,
      C_FAMILY                       => C_FAMILY
    )
    port map
    (
      SPLB_Clk                       => SPLB_Clk,
      SPLB_Rst                       => SPLB_Rst,
      PLB_ABus                       => PLB_ABus,
      PLB_UABus                      => PLB_UABus,
      PLB_PAValid                    => PLB_PAValid,
      PLB_SAValid                    => PLB_SAValid,
      PLB_rdPrim                     => PLB_rdPrim,
      PLB_wrPrim                     => PLB_wrPrim,
      PLB_masterID                   => PLB_masterID,
      PLB_abort                      => PLB_abort,
      PLB_busLock                    => PLB_busLock,
      PLB_RNW                        => PLB_RNW,
      PLB_BE                         => PLB_BE,
      PLB_MSize                      => PLB_MSize,
      PLB_size                       => PLB_size,
      PLB_type                       => PLB_type,
      PLB_lockErr                    => PLB_lockErr,
      PLB_wrDBus                     => PLB_wrDBus,
      PLB_wrBurst                    => PLB_wrBurst,
      PLB_rdBurst                    => PLB_rdBurst,
      PLB_wrPendReq                  => PLB_wrPendReq,
      PLB_rdPendReq                  => PLB_rdPendReq,
      PLB_wrPendPri                  => PLB_wrPendPri,
      PLB_rdPendPri                  => PLB_rdPendPri,
      PLB_reqPri                     => PLB_reqPri,
      PLB_TAttribute                 => PLB_TAttribute,
      Sl_addrAck                     => Sl_addrAck,
      Sl_SSize                       => Sl_SSize,
      Sl_wait                        => Sl_wait,
      Sl_rearbitrate                 => Sl_rearbitrate,
      Sl_wrDAck                      => Sl_wrDAck,
      Sl_wrComp                      => Sl_wrComp,
      Sl_wrBTerm                     => Sl_wrBTerm,
      Sl_rdDBus                      => Sl_rdDBus,
      Sl_rdWdAddr                    => Sl_rdWdAddr,
      Sl_rdDAck                      => Sl_rdDAck,
      Sl_rdComp                      => Sl_rdComp,
      Sl_rdBTerm                     => Sl_rdBTerm,
      Sl_MBusy                       => Sl_MBusy,
      Sl_MWrErr                      => Sl_MWrErr,
      Sl_MRdErr                      => Sl_MRdErr,
      Sl_MIRQ                        => Sl_MIRQ,
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
      IP2Bus_Data                    => ipif_IP2Bus_Data,
      IP2Bus_WrAck                   => ipif_IP2Bus_WrAck,
      IP2Bus_RdAck                   => ipif_IP2Bus_RdAck,
      IP2Bus_AddrAck                 => ipif_IP2Bus_AddrAck,
      IP2Bus_Error                   => ipif_IP2Bus_Error,
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
      Bus2IP_Data                    => ipif_Bus2IP_Data,
      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
      Bus2IP_BE                      => ipif_Bus2IP_BE,
      Bus2IP_Burst                   => ipif_Bus2IP_Burst,
      Bus2IP_BurstLength             => ipif_Bus2IP_BurstLength,
      Bus2IP_WrReq                   => ipif_Bus2IP_WrReq,
      Bus2IP_RdReq                   => ipif_Bus2IP_RdReq,
      Bus2IP_CS                      => ipif_Bus2IP_CS,
      Bus2IP_RdCE                    => ipif_Bus2IP_RdCE,
      Bus2IP_WrCE                    => ipif_Bus2IP_WrCE
    );

  ------------------------------------------
  -- instantiate interrupt_control
  ------------------------------------------
  INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
    generic map
    (
      C_NUM_CE                       => INTR_NUM_CE,
      C_NUM_IPIF_IRPT_SRC            => INTR_NUM_IPIF_IRPT_SRC,
      C_IP_INTR_MODE_ARRAY           => INTR_IP_INTR_MODE_ARRAY,
      C_INCLUDE_DEV_PENCODER         => INTR_INCLUDE_DEV_PENCODER,
      C_INCLUDE_DEV_ISC              => INTR_INCLUDE_DEV_ISC,
      C_IPIF_DWIDTH                  => IPIF_SLV_DWIDTH
    )
    port map
    (
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
      Bus2IP_Data                    => ipif_Bus2IP_Data,
      Bus2IP_BE                      => ipif_Bus2IP_BE,
      Interrupt_RdCE                 => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
      Interrupt_WrCE                 => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
      IPIF_Reg_Interrupts            => intr_IPIF_Reg_Interrupts,
      IPIF_Lvl_Interrupts            => intr_IPIF_Lvl_Interrupts,
      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent,
      Intr2Bus_DevIntr               => IP2INTC_Irpt,
      Intr2Bus_DBus                  => intr_IP2Bus_Data,
      Intr2Bus_WrAck                 => intr_IP2Bus_WrAck,
      Intr2Bus_RdAck                 => intr_IP2Bus_RdAck,
      Intr2Bus_Error                 => intr_IP2Bus_Error,
      Intr2Bus_Retry                 => open,
      Intr2Bus_ToutSup               => open
    );

  -- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
  intr_IPIF_Reg_Interrupts(0) <= '0';
  intr_IPIF_Reg_Interrupts(1) <= '0';
  intr_IPIF_Lvl_Interrupts(0) <= '0';
  intr_IPIF_Lvl_Interrupts(1) <= '0';
  intr_IPIF_Lvl_Interrupts(2) <= rff_FIFO2IRPT_DeadLock;
  intr_IPIF_Lvl_Interrupts(3) <= '0';

  ------------------------------------------
  -- instantiate rdpfifo_top
  ------------------------------------------
  RDPFIFO_TOP_I : entity rdpfifo_v4_02_a.rdpfifo_top
    generic map
    (
      C_OPB_PROTOCOL                 => false,
      C_MIR_ENABLE                   => false,
      C_BLOCK_ID                     => 0,
      C_NUM_REG_CE                   => RFF_NUM_REG_CE,
      C_FIFO_DEPTH_LOG2X             => RFF_FIFO_DEPTH_LOG2X,
      C_FIFO_WIDTH                   => IPIF_SLV_DWIDTH,
      C_INCLUDE_PACKET_MODE          => RFF_INCLUDE_PACKET_MODE,
      C_INCLUDE_VACANCY              => RFF_INCLUDE_VACANCY,
      C_SUPPORT_BURST                => RFF_SUPPORT_BURST,
      C_IPIF_DBUS_WIDTH              => IPIF_SLV_DWIDTH,
      C_FAMILY                       => C_FAMILY
    )
    port map
    (
      Bus_rst                        => ipif_Bus2IP_Reset,
      Bus_Clk                        => ipif_Bus2IP_Clk,
      Bus_Burst                      => ipif_Bus2IP_Burst,
      Bus_BE                         => ipif_Bus2IP_BE,
      Bus2FIFO_Reg_RdCE              => ipif_Bus2IP_RdCE(RFF_REG_CE_INDEX to    RFF_REG_CE_INDEX+RFF_NUM_REG_CE-1),
      Bus2FIFO_Data_RdCE             => ipif_Bus2IP_RdCE(RFF_DAT_CE_INDEX),
      Bus2FIFO_Reg_WrCE              => ipif_Bus2IP_WrCE(RFF_REG_CE_INDEX to    RFF_REG_CE_INDEX+RFF_NUM_REG_CE-1),
      Bus2FIFO_Data_WrCE             => ipif_Bus2IP_WrCE(RFF_DAT_CE_INDEX),
      Bus_DBus                       => ipif_Bus2IP_Data,
      Rdfifo_Pop                     => '0',
      IP2RFIFO_WrReq                 => user_IP2RFIFO_WrReq,
      IP2RFIFO_WrMark                => user_IP2RFIFO_WrMark,
      IP2RFIFO_WrRestore             => user_IP2RFIFO_WrRestore,
      IP2RFIFO_WrRelease             => user_IP2RFIFO_WrRelease,
      IP2RFIFO_Data                  => user_IP2RFIFO_Data,
      RFIFO2IP_WrAck                 => rff_RFIFO2IP_WrAck,
      RFIFO2IP_AlmostFull            => rff_RFIFO2IP_AlmostFull,
      RFIFO2IP_Full                  => rff_RFIFO2IP_Full,
      RFIFO2IP_Vacancy               => rff_RFIFO2IP_Vacancy,
      RFIFO2DMA_AlmostEmpty          => open,
      RFIFO2DMA_Empty                => open,
      RFIFO2DMA_Occupancy            => open,
      FIFO2IRPT_DeadLock             => rff_FIFO2IRPT_DeadLock,
      FIFO2Bus_DBus                  => rff_IP2Bus_Data,
      FIFO2Bus_WrAck                 => rff_IP2Bus_WrAck,
      FIFO2Bus_RdAck                 => rff_IP2Bus_RdAck,
      FIFO2Bus_Error                 => rff_IP2Bus_Error,
      FIFO2Bus_Retry                 => open,
      FIFO2Bus_ToutSup               => open
    );

  ------------------------------------------
  -- instantiate User Logic
  ------------------------------------------
  USER_LOGIC_I : entity cpt_test_v2_01_a.user_logic
    generic map
    (
      -- MAP USER GENERICS BELOW THIS LINE ---------------
      --USER generics mapped here
      -- MAP USER GENERICS ABOVE THIS LINE ---------------

      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
      C_NUM_REG                      => USER_NUM_REG,
      C_NUM_INTR                     => USER_NUM_INTR,
      C_RDFIFO_DEPTH                 => USER_RDFIFO_DEPTH
    )
    port map
    (
      -- MAP USER PORTS BELOW THIS LINE ------------------
      --USER ports mapped here
        clk => clk,
      -- MAP USER PORTS ABOVE THIS LINE ------------------

      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
      Bus2IP_Data                    => ipif_Bus2IP_Data,
      Bus2IP_BE                      => ipif_Bus2IP_BE,
      Bus2IP_RdCE                    => user_Bus2IP_RdCE,
      Bus2IP_WrCE                    => user_Bus2IP_WrCE,
      Bus2IP_Burst                   => ipif_Bus2IP_Burst,
      Bus2IP_BurstLength             => user_Bus2IP_BurstLength,
      Bus2IP_RdReq                   => ipif_Bus2IP_RdReq,
      Bus2IP_WrReq                   => ipif_Bus2IP_WrReq,
      IP2Bus_AddrAck                 => user_IP2Bus_AddrAck,
      IP2Bus_Data                    => user_IP2Bus_Data,
      IP2Bus_RdAck                   => user_IP2Bus_RdAck,
      IP2Bus_WrAck                   => user_IP2Bus_WrAck,
      IP2Bus_Error                   => user_IP2Bus_Error,
      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent,
      IP2RFIFO_WrReq                 => user_IP2RFIFO_WrReq,
      IP2RFIFO_Data                  => user_IP2RFIFO_Data,
      IP2RFIFO_WrMark                => user_IP2RFIFO_WrMark,
      IP2RFIFO_WrRelease             => user_IP2RFIFO_WrRelease,
      IP2RFIFO_WrRestore             => user_IP2RFIFO_WrRestore,
      RFIFO2IP_WrAck                 => rff_RFIFO2IP_WrAck,
      RFIFO2IP_AlmostFull            => rff_RFIFO2IP_AlmostFull,
      RFIFO2IP_Full                  => rff_RFIFO2IP_Full,
      RFIFO2IP_Vacancy               => rff_RFIFO2IP_Vacancy
    );

  ------------------------------------------
  -- connect internal signals
  ------------------------------------------
  IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data, rff_IP2Bus_Data ) is
  begin

    case ipif_Bus2IP_CS is
      when "1000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
      when "0100" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
      when "0010" => ipif_IP2Bus_Data <= rff_IP2Bus_Data;
      when "0001" => ipif_IP2Bus_Data <= rff_IP2Bus_Data;
      when others => ipif_IP2Bus_Data <= (others => '0');
    end case;

  end process IP2BUS_DATA_MUX_PROC;

  ipif_IP2Bus_AddrAck <= ipif_Bus2IP_Burst and user_IP2Bus_AddrAck;
  ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck or rff_IP2Bus_WrAck;
  ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck or rff_IP2Bus_RdAck;
  ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error or rff_IP2Bus_Error;

  user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
  user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);

  user_Bus2IP_BurstLength(8-log2(16*(C_SPLB_DWIDTH/8)) to 8) <= ipif_Bus2IP_BurstLength;

end IMP;

 

Thanks for your help

 

CC

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golson
Scholar
Scholar
7,028 Views
Registered: ‎04-07-2008

Hi,

  I took a look at your code.  I never used a 128 width Native Width which you used here.  But I also believe you have not

It looks like to me wrreq is not driven, and also the Data port does not being driven with a pattern.

 

When I did my designs,  I would use a outside fifo to feed the rpfifo with data so I would use data signals from the outside fifo (let me say coregen generated fifo) which would hook up the data to the rpfifo.  That would feed the data lines.  and I had code which would create the write request signal the the rpfifo.  this code would check for fifo full conditions so that it would not overwrite the

fifo.

 

I am not seeing these signals being driven in your design. 

 

I am not sure how  to handle the 128 width though.  I was using 32 bit wide native width compared to you 128 bit wide width.

 

For your information here is my top level code.  Some of my logic is not inside this module though.

 

entity ipif_dmavac is

generic

(

-- ADD USER GENERICS BELOW THIS LINE ---------------

--USER generics added here

-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------

-- Bus protocol parameters, do not add to or delete

C_BASEADDR : std_logic_vector := X"FFFFFFFF";

C_HIGHADDR : std_logic_vector := X"00000000";

C_SPLB_AWIDTH : integer := 32;

C_SPLB_DWIDTH : integer := 128;

C_SPLB_NUM_MASTERS : integer := 8;

C_SPLB_MID_WIDTH : integer := 3;

C_SPLB_NATIVE_DWIDTH : integer := 32;

C_SPLB_P2P : integer := 0;

C_SPLB_SUPPORT_BURSTS : integer := 1;

C_SPLB_SMALLEST_MASTER : integer := 32;

C_SPLB_CLK_PERIOD_PS : integer := 10000;

C_INCLUDE_DPHASE_TIMER : integer := 1;

C_FAMILY : string := "virtex6"

-- DO NOT EDIT ABOVE THIS LINE ---------------------

);

port

(

-- ADD USER PORTS BELOW THIS LINE ------------------

--USER ports added here

-- ADD USER PORTS ABOVE THIS LINE ------------------

ADV_WFIFO2IP_Data &colon; out STD_LOGIC_VECTOR(0 to 31);

ADV_WFIFO2IP_RdAck : out STD_LOGIC;

ADV_WFIFO2IP_empty : out STD_LOGIC;

ADV_IP2WFIFO_RdReq : in STD_LOGIC;

ADV_WFIFO2IP_Occupancy : out std_logic_vector(0 to 9); -- WFF_FIFO_DEPTH_LOG2X);

----------------------------------------------------

ADV_RFIFO2IP_AlmostFull : out STD_LOGIC;

ADV_RFIFO2IP_Full : out STD_LOGIC;

ADV_IP2RFIFO_Data &colon; in STD_LOGIC_VECTOR(0 to 31);

ADV_IP2RFIFO_WrReq : in STD_LOGIC;

ADV_RFIFO2IP_WrAck : out STD_LOGIC;

ADV_RFIFO2IP_Vacancy : out std_logic_vector(0 to 9); --RFF_FIFO_DEPTH_LOG2X);

----------------------------------------------------

 

-- DO NOT EDIT BELOW THIS LINE ---------------------

-- Bus protocol ports, do not add to or delete

SPLB_Clk : in std_logic;

SPLB_Rst : in std_logic;

PLB_ABus : in std_logic_vector(0 to 31);

PLB_UABus : in std_logic_vector(0 to 31);

PLB_PAValid : in std_logic;

PLB_SAValid : in std_logic;

PLB_rdPrim : in std_logic;

PLB_wrPrim : in std_logic;

PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);

PLB_abort : in std_logic;

PLB_busLock : in std_logic;

PLB_RNW : in std_logic;

PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);

PLB_MSize : in std_logic_vector(0 to 1);

PLB_size : in std_logic_vector(0 to 3);

PLB_type : in std_logic_vector(0 to 2);

PLB_lockErr : in std_logic;

PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);

PLB_wrBurst : in std_logic;

PLB_rdBurst : in std_logic;

PLB_wrPendReq : in std_logic;

PLB_rdPendReq : in std_logic;

PLB_wrPendPri : in std_logic_vector(0 to 1);

PLB_rdPendPri : in std_logic_vector(0 to 1);

PLB_reqPri : in std_logic_vector(0 to 1);

PLB_TAttribute : in std_logic_vector(0 to 15);

Sl_addrAck : out std_logic;

Sl_SSize : out std_logic_vector(0 to 1);

Sl_wait : out std_logic;

Sl_rearbitrate : out std_logic;

Sl_wrDAck : out std_logic;

Sl_wrComp : out std_logic;

Sl_wrBTerm : out std_logic;

Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);

Sl_rdWdAddr : out std_logic_vector(0 to 3);

Sl_rdDAck : out std_logic;

Sl_rdComp : out std_logic;

Sl_rdBTerm : out std_logic;

Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);

Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);

Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);

Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)

-- DO NOT EDIT ABOVE THIS LINE ---------------------

);

 

.....

 

 

------------------------------------------

-- instantiate rdpfifo_top

------------------------------------------

RDPFIFO_TOP_I : entity rdpfifo_v4_02_a.rdpfifo_top

generic map

(

C_OPB_PROTOCOL => false,

C_MIR_ENABLE => false,

C_BLOCK_ID => 0,

C_NUM_REG_CE => RFF_NUM_REG_CE,

C_FIFO_DEPTH_LOG2X => RFF_FIFO_DEPTH_LOG2X,

C_FIFO_WIDTH => IPIF_SLV_DWIDTH,

C_INCLUDE_PACKET_MODE => RFF_INCLUDE_PACKET_MODE,

C_INCLUDE_VACANCY => RFF_INCLUDE_VACANCY,

C_SUPPORT_BURST => RFF_SUPPORT_BURST,

C_IPIF_DBUS_WIDTH => IPIF_SLV_DWIDTH,

C_FAMILY => C_FAMILY

)

port map

(

Bus_rst => rst_Bus2IP_Reset,

Bus_Clk => ipif_Bus2IP_Clk,

Bus_Burst => ipif_Bus2IP_Burst,

Bus_BE => ipif_Bus2IP_BE,

Bus2FIFO_Reg_RdCE => ipif_Bus2IP_RdCE(RFF_REG_CE_INDEX to RFF_REG_CE_INDEX+RFF_NUM_REG_CE-1),

Bus2FIFO_Data_RdCE => ipif_Bus2IP_RdCE(RFF_DAT_CE_INDEX),

Bus2FIFO_Reg_WrCE => ipif_Bus2IP_WrCE(RFF_REG_CE_INDEX to RFF_REG_CE_INDEX+RFF_NUM_REG_CE-1),

Bus2FIFO_Data_WrCE => ipif_Bus2IP_WrCE(RFF_DAT_CE_INDEX),

Bus_DBus => ipif_Bus2IP_Data,

Rdfifo_Pop => '0',

IP2RFIFO_WrReq => ADV_IP2RFIFO_WrReq, --user_IP2RFIFO_WrReq, Gary

IP2RFIFO_WrMark => '0',

IP2RFIFO_WrRestore => '0',

IP2RFIFO_WrRelease => '0',

IP2RFIFO_Data => ADV_IP2RFIFO_Data, --user_IP2RFIFO_Data, Gary

RFIFO2IP_WrAck => ADV_RFIFO2IP_WrAck, -- rff_RFIFO2IP_WrAck, Gary

RFIFO2IP_AlmostFull => ADV_RFIFO2IP_AlmostFull, --rff_RFIFO2IP_AlmostFull, Gary

RFIFO2IP_Full => ADV_RFIFO2IP_Full, --rff_RFIFO2IP_Full, Gary

RFIFO2IP_Vacancy => ADV_RFIFO2IP_Vacancy, --rff_RFIFO2IP_Vacancy, Gary

RFIFO2DMA_AlmostEmpty => open,

RFIFO2DMA_Empty => open,

RFIFO2DMA_Occupancy => open,

FIFO2IRPT_DeadLock => open,

FIFO2Bus_DBus => rff_IP2Bus_Data,

FIFO2Bus_WrAck => rff_IP2Bus_WrAck,

FIFO2Bus_RdAck => rff_IP2Bus_RdAck,

FIFO2Bus_Error => rff_IP2Bus_Error,

FIFO2Bus_Retry => open,

FIFO2Bus_ToutSup => open

);

 

Hope this helps you,

Gary

 

 

 

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cchamp
Participant
Participant
7,020 Views
Registered: ‎07-11-2011

The signals you mentioned are driven in my user_logic file. My data are well written in the FIFO I just can read them all with Microblaze

Thanks

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nbroyer
Visitor
Visitor
837 Views
Registered: ‎07-20-2018

I know this has been almost 6 years, but did you ever resolve this? If you did, do you happen to remember what the solution was? I'm having the same exact problem. Thanks!

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