Read FPGA clock frequency in software

[vgokhale]

Hello,

Is there any way to query the frequency that the FCLK0-3 are running at? 

I have read that there are certain registers that need to be written to that then set the divider and output the correct frequency but I believe this would be done by the FSBL at boot time. Is there any way to read these registers?

I basically want to know in software, what frequency the PL is operating at.

Thank you.

[muzaffer]

read chapter 25 of the TRM (ug585) specifically section 25.9.

[willparker]

Are the system clock frequencies available in xparameters.h. (generated as part of the BSP)?

UG647 implies that xparameters.h does provide this information to C applications : "the processor frequency (in Hz) is defined in xparameters.h". (page 57).

In xparameters.h, I find a #define statement as follows: "#define XPAR_CORE_CLOCK_FREQ_HZ  12500000" 

Is this the system clock frequency that all of the PLL's for the peripherals reference?

Also, are there any reference designs or examples showing that the read/write to PS side registers look like in software?

Thank You

[trenz-al]

Frequency of FCLK0-3 are set in FSBL during init of the PS registers, with recent linux kernels it is possible to chagne or query those frequencies from linux userland.

To your question there is no answer, the PL buses can run at different clock, those clocks can come from FCLKx but do not need, it is up to your design how the clocking is implemented.

[johnsusitronix]

The code generated when eclipse imports the system.hdf file, the PL clock frequencies can be found in "ps7_init.h"