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Observer
Observer
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Registered: ‎11-08-2017

Read Zynq UART1 I/O Periph from PL side

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Hi all,

We've got a PCB that communicates with UART1 with another device. This external device trasmits at 921600 bps (92.16 Bytes/ms) and the UART1 internal buffer is of 64 bytes. We are polling this UART1 every 10 ms, we cannot polling lower.

Looking at Zynq scheme, UART1 is connected to PS via AXI. Is it possible to UART1 to PL via AXI to create an intermediate FIFO much higher than 64 bytes?

If answer is yes, do yo recommend handle complete UART1 from PL?  or can we write using the PS and read using the PL?

Thanks in advance,

Regards.

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Scholar
Scholar
130 Views
Registered: ‎06-10-2008

I see no reason why it would not be possible to access the PS UART peripheral over one of the S_AXI_GP ports. See also UG585 par. 5.5. Further you can also bring the IRQ_P2F_UART to the PL. Once you do that I recommend not to also use the interrupt in the PS. If you're fine with transmitting in a polling way that is still possible though.

But polling is not a great way of handling almost any peripheral. Try to recover from your interruptiphobia and start using interrupts.Fill a deeper software FIFO in your ISR (interrupt service routine). You will most probably find that you do not need the PL to tackle this.

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Moderator
Moderator
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Registered: ‎04-09-2019

Hi,

Looks UART1 from PS is connected only through EMIO lines due to the shortage of MIO lines in the PS section, but it does not have any kind of controller information in the PL part so it is not possible from PL .

Regards,

Venu

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Observer
Observer
146 Views
Registered: ‎11-08-2017

What about the APB bus connected to the controller. Can it be accessed from PL?

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Scholar
Scholar
131 Views
Registered: ‎06-10-2008

I see no reason why it would not be possible to access the PS UART peripheral over one of the S_AXI_GP ports. See also UG585 par. 5.5. Further you can also bring the IRQ_P2F_UART to the PL. Once you do that I recommend not to also use the interrupt in the PS. If you're fine with transmitting in a polling way that is still possible though.

But polling is not a great way of handling almost any peripheral. Try to recover from your interruptiphobia and start using interrupts.Fill a deeper software FIFO in your ISR (interrupt service routine). You will most probably find that you do not need the PL to tackle this.

View solution in original post

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Observer
Observer
121 Views
Registered: ‎11-08-2017

Thanks for the advise.

I was only want to see if it was possible to rely on hardware to handle all this. We part from an existing and tested scheduling, and maybe the FPGA solution will save us resources.

This is not interruptfobia, this is determinismphilia  

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