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jmcanals98
Visitor
Visitor
2,496 Views
Registered: ‎02-16-2019

Read and write through AXI4

Hi, I'm a begginer in VHDL and I  need to stablish communication between a memory and a MIG through AXI4 interface. To begin with my problem I want to do a very basic program in which I write something simple like '1010' into the memory from the MIG and after that, read from the memory that '1010'. My main problem is that I don't find any tutorial or example code in which I can see how to read and write

Please, a tutorial or an example code would be very helpful.

 

Thank you

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

I've recently written several blog articles on the topic of AXI.  This includes a articles examining Xilinx's AXI-lite slave demonstration core, their AXI slave demonstrator, examples of how to build both AXI-lite and AXI slaves, how to verify them, common bugs found when verifying AXI cores, etc.  I also needed to present a discussion of skid buffers (you'll need them), as well as a description of how AXI addressing works.

I'll admit, none of these articles really presents a "how to build an AXI master".   To some extent this is because bus masters tend to be bridges from other protocols.  So, for example, I have example code to convert from AXI-lite to AXI, AXI to AXI-lite, Wishbone (WB) to AXI, AXI-lite to WB, etc.  Indeed, whenever I need to drive an AXI slave myself--such as the MIG generated IP core, I typically use a WB to AXI converter, if for no other reason than I find WB easier to work with.

You can find the blog posts on ZipCPU.com, and the examples in my WB2AXIP repository on github.  You'll also find a discussion of how to build a WB master--which just bridges from a UART based protocol ...

Dan

jmcanals98
Visitor
Visitor
1,460 Views
Registered: ‎02-16-2019

Thank you Dan, but I need something easier. I think that I don't need such a level of detail to do what I want. At the moment, I'm creating a custom AXI4 peripheral with the wizard and I'm trying to understand what to do with the files that Vivado Generates. I see a line in the code which says: --add user logic here--

But I don't know how to handle it. I mean, i just want to know how to send "111111111..." to a BRAM through AXI and after that, read all those 1s that I've written on my memory. Hope that it's something easier.
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dgisselq
Scholar
Scholar
1,423 Views
Registered: ‎05-21-2015

In many ways, it's a shame Xilinx chose AXI as their protocol for connecting everything together.  AXI is a very complicated protocol, and a hard one to get right.  I like to use Wishbone, and find it much easier to work with.  There's also an AHB protocol that's easier to work with than Wishbone.

That said, I really don't know any way to make this "easy" as you would like.  The complexity comes with the territory.

Sorry,

Dan

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vanmierlo
Mentor
Mentor
1,401 Views
Registered: ‎06-10-2008

I suggest to start with trying to make an AXI-lite master to write and read the memory. It is a much simpler protocol than full AXI. And if you don't need the performance of full AXI, stay with AXI-lite.

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ash_dudeja
Adventurer
Adventurer
1,314 Views
Registered: ‎01-14-2009

There are example designs available for almost every axi block that we include in our project . i. e. MIG.

Yes , you need to go a bit deep inside the logic written ,where you edit user logic.

But if you have a basic understanding of vhdl/verilog you can see how this logic is written.

A simple traffic Generator is also given for MIG, which falls in line with your requirement "1010" etc.

 

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