07-22-2019 01:37 AM
Hi, I'm a begginer in VHDL and I need to stablish communication between a memory and a MIG through AXI4 interface. To begin with my problem I want to do a very basic program in which I write something simple like '1010' into the memory from the MIG and after that, read from the memory that '1010'. My main problem is that I don't find any tutorial or example code in which I can see how to read and write.
Please, a tutorial or an example code would be very helpful.
07-22-2019 06:41 PM
I've recently written several blog articles on the topic of AXI. This includes a articles examining Xilinx's AXI-lite slave demonstration core, their AXI slave demonstrator, examples of how to build both AXI-lite and AXI slaves, how to verify them, common bugs found when verifying AXI cores, etc. I also needed to present a discussion of skid buffers (you'll need them), as well as a description of how AXI addressing works.
I'll admit, none of these articles really presents a "how to build an AXI master". To some extent this is because bus masters tend to be bridges from other protocols. So, for example, I have example code to convert from AXI-lite to AXI, AXI to AXI-lite, Wishbone (WB) to AXI, AXI-lite to WB, etc. Indeed, whenever I need to drive an AXI slave myself--such as the MIG generated IP core, I typically use a WB to AXI converter, if for no other reason than I find WB easier to work with.
You can find the blog posts on ZipCPU.com, and the examples in my WB2AXIP repository on github. You'll also find a discussion of how to build a WB master--which just bridges from a UART based protocol ...
07-23-2019 07:56 AM
07-29-2019 04:33 AM
In many ways, it's a shame Xilinx chose AXI as their protocol for connecting everything together. AXI is a very complicated protocol, and a hard one to get right. I like to use Wishbone, and find it much easier to work with. There's also an AHB protocol that's easier to work with than Wishbone.
That said, I really don't know any way to make this "easy" as you would like. The complexity comes with the territory.
07-30-2019 02:07 AM
I suggest to start with trying to make an AXI-lite master to write and read the memory. It is a much simpler protocol than full AXI. And if you don't need the performance of full AXI, stay with AXI-lite.
08-18-2019 09:54 PM
There are example designs available for almost every axi block that we include in our project . i. e. MIG.
Yes , you need to go a bit deep inside the logic written ,where you edit user logic.
But if you have a basic understanding of vhdl/verilog you can see how this logic is written.
A simple traffic Generator is also given for MIG, which falls in line with your requirement "1010" etc.