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Scholar
Scholar
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Registered: ‎05-14-2017

Reading contiguous 64 MB from AXI DMA direct mode

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Hi,

I am trying to read contiguous 64 MB from AXI DMA configured in direct mode but I am facing a DMA behaviour problem that I think is not coherent to what the PG021 says.

In chapter 4 the doc says:

Width of Buffer Length Register

This integer value specifies the number of valid bits used for the Control field buffer length and Status field bytes transferred in the Scatter/Gather descriptors. It also specifies the number of valid bits in the RX Length of the Status Stream App4 field when Use Rxlength is enabled. For Direct Register Mode, it specifies the number of valid bits in the MM2S_LENGTH and S2MM_LENGTH registers. The length width directly correlates to the number of bytes being specified in a Scatter/Gather descriptor or number of bytes being specified in App4.RxLength, MM2S_LENGTH, or  S2MM_LENGTH. The number of bytes is equal to 2^{Length Width}. So a Length Width of 26 gives a byte count of 67,108,863 bytes. This value should be set to 23 for Multichannel mode.

So, if from the S2MM side the data width is 32 bits, with the register length set to  26 I issue a TLAST every 16777216 clock cycles.

But on PS side, instead of reading contiguous 64 MB I can only read 8 MB.

Can someone clarify if my understanding is wrong or not ?

Thanks,

s.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @simozz ,

Usually when one says they want to read with AXI DMA, this means they are trying to perform an MM2S transfer. It sounds like you are more concerned with performing a S2MM transfer where you write the data to DDR.

The width of the buffer length register establishes what your maximum transfer size can be in bytes. It seems like your understanding of how to set this value in the AXI DMA configuration GUI is correct.

When you set up your S2MM transfer in direct mode, what value are you putting in the S2MM_LENGTH register at offset 0x58?

What do you read back from S2MM_LENGTH when your transfer completes?

Regards,

Deanna

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @simozz ,

Usually when one says they want to read with AXI DMA, this means they are trying to perform an MM2S transfer. It sounds like you are more concerned with performing a S2MM transfer where you write the data to DDR.

The width of the buffer length register establishes what your maximum transfer size can be in bytes. It seems like your understanding of how to set this value in the AXI DMA configuration GUI is correct.

When you set up your S2MM transfer in direct mode, what value are you putting in the S2MM_LENGTH register at offset 0x58?

What do you read back from S2MM_LENGTH when your transfer completes?

Regards,

Deanna

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Scholar
Scholar
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Registered: ‎05-14-2017

Hello @demarco ,

Thank you for ensuring about my interpretation. You are right, I am talking about S2MM.

Regarding to the 8 MB I noticed that I had a mistake in my userspace code which was limiting S2MM_LENGHT.

Having this error corrected, with TLAST count set to 16777216, I write 0x03ffffff and I read back the same value from S2MM_LENGHT, but I also detect the DMASlvErr, DMADecErr and Dly_Irq.

From DMA's DS, DMASlvErr and DMADecErr remind me to memory mapping issues.

In my petalinux settings I reserved the upper 512 MB of the RAM from system-user.dtsi as follows:

  memory {
    device_type = "memory";
    reg = <0x0 0x0 0x0 0x60000000>;
  };

But I am not sure this is the problem.

s.

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Scholar
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Registered: ‎05-14-2017

Also, what is strange is that in DR mode Dly_Irq is kept in account, while datasheet says, for S2MM_DMACR[13] that

This bit is ignored when AXI DMA is configured for Direct Register Mode.

and

This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.

for S2MM_DMASR[13]. And I can confirm, of course, that AXI DMA is operating in DR mode.

s.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @simozz ,

Can you simplify this a bit and see if this works in a bare metal software application? You're getting so many errors and I'm not sure if your hardware is stable.

The combination of DecErr and SlvErr is concerning. Getting a SlvErr on a write is pretty unusual, unless you are doing an unaligned access to a memory with ECC.

The DecErr suggests that there is something wrong in how you are allocating the buffer to write to or you are giving the AXI DMA a virtual address rather than a physical address to work on. These usually originate from an interconnect when it cannot decode the address in the AXI command.

I'm not sure why you are getting a Dly_Irq. This makes me think your hardware design has some other issue. I would expect to see bit 14 of the S2MM_DMASR register asserted based on the other errors.

You may also consider addings ILAs to the S_AXI_LITE and M_AXI_S2MM interfaces to ease debug.

Regards,

Deanna

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Scholar
Scholar
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Registered: ‎05-14-2017

Hi @demarco ,

The system works fine if I set the HW to receive 8 MB per packet (32 bits and TLAST every 2097152 clock cycles). This makes me think that the design should be stable.

I will post some simulation as soon as possible.

s.

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Scholar
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Registered: ‎05-14-2017

@demarco ,

The problem I was facing was due to a small bug in the userspace code.

I can receive the 64 MB all at once, however I think that with these amount of chunks memory must be CMA. udmabuf should do the trick in this case from userspace.

However I can consider the problem of the first message to be solved.

Regards,

s.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @simozz ,

You are correct: to use the AXI DMA direct mode, the 64MB chunk the OS allocates needs to be contiguous. I'm glad you found the error in your code and were able to resolve the problem.

Regards,

Deanna

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Scholar
Scholar
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Registered: ‎05-14-2017

Well, I don't think it is solved at all

https://forums.xilinx.com/t5/Processor-System-Design/Reading-contiguous-64-MB-from-AXI-DMA-direct-mode-2019-2-2/m-p/1075703/highlight/true#M51413

I am not sure it is a problem of CMA. I think that misaligned data is a result of the problem described in the linked post.

Regards.

s.

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