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derickshi
Adventurer
Adventurer
957 Views
Registered: ‎11-25-2015

Reading data from HP slave port fails

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Hello community,

 

I've been struggle on this problem for 2 days. I'm trying to implement a simple demo project on my ZC706 board. Here is what I'm trying to do: I have a simple HLS IP core which has 2 full AXI4 interfaces. One of the AXI4 interface reads data from PS DDR through HP slave port, and another AXI4 interface reads data from PL DDR through MIG IP core. The IP core is configured by the GP0 port of PS:

 

Capture.PNG

 

I modified my linker script so that all the executable and stack/heap are on PS DDR. The OS I'm using now is standalone OS. Below is my software code:

 

#define ARRAY_SIZE 32

int main()
{
    // Initialize input vectors in PS DDR
    int test_a[ARRAY_SIZE];
    int test_b[ARRAY_SIZE];
    for(int i=0;i<ARRAY_SIZE;i++){
    	test_a[i] = i;
	test_b[i] = i;
    }
    // Copy vector b from PS DDR to PL DDR
    int *test_c;
    test_c = (int *)0x80000000; // address of test_c vector
    memcpy(test_c,test_b,ARRAY_SIZE*sizeof(int));

    // configure IP core
    XVecdotprod instVecdotprod;
    XVecdotprod_Config *instVecdotprod_Config;
    instVecdotprod_Config = XVecdotprod_LookupConfig(XPAR_VECDOTPROD_0_DEVICE_ID);
    if(!instVecdotprod_Config){
    	xil_printf("\nError loading config for instVecdotprod_Config!\n");
    }
    int status = XVecdotprod_CfgInitialize(&instVecdotprod,instVecdotprod_Config);
    if(status != XST_SUCCESS){
    	xil_printf("\nError initializing for instVecdotprod!\n");
    }
	
    // set offset address
    XVecdotprod_Set_v1_in(&instVecdotprod,u32(test_a)); //PS DDR
    XVecdotprod_Set_v2_in(&instVecdotprod,0x80000000); //PL DDR
	
    // start IP core execution
    XVecdotprod_Start(&instVecdotprod);

    // wait until it is done
    while (!XVecdotprod_IsDone(&instVecdotprod));

    u32 u_result = XVecdotprod_Get_vout(&instVecdotprod);
    int result = int(u_result);

    /* Compute golden output */
    int golden_result = 0;
    for(int i=0;i<ARRAY_SIZE;i++){
    	golden_result += test_a[i] * test_c[i];
    }
	
    return 0;
}

 

The software result is correct which means that 'test_b' is successfully copied from PS to PL. I use ILA to watch the signals on the AXI4 interfaces, I found that the address offset is set correctly, and data reading from PL DDR are also correct, but data reading from PS DDR are just random garbage:

Capture.PNG

 

I have no clue what is going on. Can anyone help please?

 

Many thanks,

Derick

 

  

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1 Solution

Accepted Solutions
johnmcd
Xilinx Employee
Xilinx Employee
1,131 Views
Registered: ‎02-01-2008

A9 writing to PS DDR is probably cached. Try flushing the cache after app writes to PS DDR to make sure the data is actually written to DDR.

 

And same going the other direction. If PL is writing to PS DDR via HP, have the A9 invalidate cache before reading the PS DDR.

View solution in original post

2 Replies
johnmcd
Xilinx Employee
Xilinx Employee
1,132 Views
Registered: ‎02-01-2008

A9 writing to PS DDR is probably cached. Try flushing the cache after app writes to PS DDR to make sure the data is actually written to DDR.

 

And same going the other direction. If PL is writing to PS DDR via HP, have the A9 invalidate cache before reading the PS DDR.

View solution in original post

derickshi
Adventurer
Adventurer
933 Views
Registered: ‎11-25-2015
@johnmcd THANK YOU! I called Xil_DCacheFlush() before starting my accelerator and I get the correct result. You save my day.
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