Receiving error: [BD 41-237] Bus Interface property FREQ_HZ does not match" When updating a custom AXI IP
I am currently creating a memory controller axi component and trying to test it by writing to a BRAM. I'm running my design on a Zedboard and using the ZYNQ processor. I am running all my components on the FCLK_CLK0 and I changed the frequency to 50 MHz to meet timing requirements. This setup works fine with no issues when I create a new project with my custom IP. However, as soon as I make any changes to my custom IP and run "Upgrade IP," I receive this error
"[BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_smc_1/S00_AXI(50000000) and /memsec_0/m_axi(100000000)"
If I rebuild the block diagram it works fine again, but because I am doing active development this is impractical and takes way too much time. I can't find a good solution for this, as apparently the FREQ_HZ parameter is read-only and it won't let me modify it to 50 MHz manually... Is there anything I can do to work around this?