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pranju
Adventurer
Adventurer
3,849 Views
Registered: ‎04-11-2018

Regarding interface between PS and PL

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Hi,

I have some knowledge regarding FPGAs. I need help regarding the transfer of data from PS to PL. I have seen videos and read articles regarding the communication between PS and PL. I am unable to comprehend and unclear as it involves the DMA transfer, DDR memory, BRAM, etc. I have the Zynq 7000 series board with petalinux kernel running ROS and OpenCV. I want to capture the image from the USB camera and forward it to the PL for further processing and make use of hardware acceleration.Can someone please provide an idea to proceed with it?

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savula
Moderator
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3,958 Views
Registered: ‎10-30-2017

Hi @pranju,

 

there are different interconnects are available for PS PL communication in Zynq:

1.  CPUs and accelerator coherency port (ACP)
2.  High performance PL interfaces, AXI_HP{3:0}
3.  General purpose PL interfaces, AXI_GP{1:0}
4.  DMA controller
5.  AHB masters (I/O peripherals with local DMA units)
6.  Device configuration (DevC) and debug access port (DAP)

These ports are used to transfer the data between the PS and PL.

Please read the Chapter 5 in ug585 (zynq 7000 TRM).

 

coming to your application, there is a similar type of xapp (xapp1205) is available which demonstrates the VDMA and PS PL communication using the HP ports.

this xapp will helps you to understand and develop the PS PL communication.

https://www.xilinx.com/support/documentation/application_notes/xapp1205-high-performance-video-zynq.pdf

 

 

Best Regards,
Srikanth
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9 Replies
savula
Moderator
Moderator
3,959 Views
Registered: ‎10-30-2017

Hi @pranju,

 

there are different interconnects are available for PS PL communication in Zynq:

1.  CPUs and accelerator coherency port (ACP)
2.  High performance PL interfaces, AXI_HP{3:0}
3.  General purpose PL interfaces, AXI_GP{1:0}
4.  DMA controller
5.  AHB masters (I/O peripherals with local DMA units)
6.  Device configuration (DevC) and debug access port (DAP)

These ports are used to transfer the data between the PS and PL.

Please read the Chapter 5 in ug585 (zynq 7000 TRM).

 

coming to your application, there is a similar type of xapp (xapp1205) is available which demonstrates the VDMA and PS PL communication using the HP ports.

this xapp will helps you to understand and develop the PS PL communication.

https://www.xilinx.com/support/documentation/application_notes/xapp1205-high-performance-video-zynq.pdf

 

 

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
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yetanotherid
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Registered: ‎12-08-2014

@pranju you have a long road ahead of you. In broad-brush terms, you'll place an AXI DMA block in the PL connected to the HP0 port, since that provides the PL with direct access to the DDR memory. Downstream from that will be HDL or IP that receives the image data (probably in a line-by-line fashion) and does the processing. This process is kicked off from the PS by using the AXI DMA block's driver to initiate the data transfer. The PS then busy-waits or uses interrupts to determine when the DMA block has finished pushing the results back to the DDR memory. PS then invalidates that portion of the cache and can read the results.

 

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pranju
Adventurer
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Registered: ‎04-11-2018

@savulaThank you so much. Besides that, I have OpenCV running on Zynq Z7030 board. I wanted to know if I can install Xilinx opencv? I know it is compatible with SDSoC 2018 and operates on Zynq and tested on ZCU102 and ZCU 104 boards. Whereas, I am working with Vivado 2017.4.

 

Regarding my application, I am able to capture the image and now I want to transfer it to FPGA. Just to clarify, I have to design a block diagram in Vivado and write the hdl code for the blocks and the operation will be written in SDK,right? In the block design I will be having the Zynq processing system and the microblaze so as to communicate between the PS and the PL.

Am I thinking, right?

 

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pranju
Adventurer
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Registered: ‎04-11-2018

@yetanotheridThank you so very much!

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betanken
Adventurer
Adventurer
3,520 Views
Registered: ‎08-22-2018

Hallo, @pranju

 

have you finally found out have to do this?

 

Thanks a lot

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2,835 Views
Registered: ‎04-10-2019
Hello ,
I have ROS on the PS and I have a block design on Vivado which needs to be loaded on the PL and establish communication between ROS , the IP and gazebo but I can't do the step of loading my IP using Petalinux ,can you please help ?
Mohamed Taher
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nju0441
Observer
Observer
1,397 Views
Registered: ‎02-06-2018
Hi mohamed,
Did you run ROS on ubuntu or just on petalinux-built linux?
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nju0441
Observer
Observer
1,392 Views
Registered: ‎02-06-2018

Hi pranju,

Could you please share a concise flow of implementing "Zynq 7000 series board with petalinux kernel running ROS and OpenCV"?

 

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simoneeic
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Registered: ‎02-11-2020
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