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mnanoop2014
Participant
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Registered: ‎10-29-2018

Regarding reading/writing to registers on AXI lite bus

EDIT: I am able to read and write to registers hanging on the mmi64_axi bus when I use the same clock as the processor is running on (100MHz). When everything else is same except I use a generated clock of 8Mhz, and a push button Reset, the system doesn't work. I can provide more information if needed. Any idea where I might be going wrong with this one?

 

I have the following setup in Vivado IPI:

I want to read and write to the registers of the AXI port I've made external through baremetal apps first and then through linux. I know the address map of it through Address Editor. How should I go about with it? I tried looking for xilinx header files for functions to read and write. I am not able to find it. Any help is appreciatedScreenshot from 2019-01-08 11-08-01.png

 More info: clk_out1 is 8 MHz. I tried accessing the registers through __raw_readl in linux kernel module, but the board's linux system just hangs and I've to reboot the board again.

I can provide more information 

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florentw
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Registered: ‎11-09-2015

Hi @mnanoop2014,

From the linux userspace, you can use devmem to access the physical memory of your device.

Hope that helps,

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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stephenm
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Registered: ‎09-12-2007

I dont think there is a register space for the AXI clock Converter. The config is done in the HW in the IPI design

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tedbooth
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Registered: ‎03-28-2016

For bare-metal software, you can use the IO functions defined in xil_io.h.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
mnanoop2014
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Registered: ‎10-29-2018

Yes thank you. I tried functions under "xil_io.h" to try to access the registers successfully. I am unable to read and write to registers when I use a separate clock and reset to drive my axi peripheral. Any idea why that might be so?
Thanks
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florentw
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Registered: ‎11-09-2015

Hi @mnanoop2014,

Are you sure your other clock is up? And the polarity of the reset signal is correct?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mnanoop2014
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Registered: ‎10-29-2018

Yes, I have verified the clock by feeding it to a 32 bit counter and connecting the 28th bit or something to an led. I have tried with both active high and active low. Neither of those changes alone works.
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dgisselq
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Registered: ‎05-21-2015

Have you tried this technique at all to see if your AXI-lite slave works in the first place?

Dan

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mnanoop2014
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Registered: ‎10-29-2018

Hi Dan, 

I have tried a similar simple example, but with the processor clock as the clock feeding my peripheral. Now, however, I am trying to use a smaller 8 MHz clock and push-button reset. I am not sure where I am going wrong. Any suggestions or clues?

I will also look into the link you sent meanwhile.

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tedbooth
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Registered: ‎03-28-2016

Are you following these AXI-Lite clock requirements from UG902?

• AXI4-Lite interface clock must be synchronous to the clock used for the synthesized logic (ap_clk). That is, both clocks must be derived from the same master generator clock.

• AXI4-Lite interface clock frequency must be equal to or less than the frequency of the clock used for the synthesized logic (ap_clk).

I've had issues with the AXI-Lite interfaces on HLS cores when I didn't follow those requirements.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
mnanoop2014
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Registered: ‎10-29-2018

Hi @tedbooth
The AXI based port (mmi64_axi in the diagram) uses a clock derived from an external source (noc_clk) and the same clock (noc_clk) is used for the logic inside it.
However, there is also a clock converter used as shown in the figure.
Do you mean I have to derive the clock for the AXI interface from (pl_clk0)?
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