cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
1,043 Views
Registered: ‎09-23-2018

Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hello,

I used the standard example from the axi_ethernet directory (xaxiethernet_example_intr_sgdma) for AXI DMA in scatter gather mode. I could transmit and receive a packet.

Later, I modified the code to receive the data in promiscuous mode. I could see a single packet again. Could anyone let me know the modifications that would be required in the code to receive the packets continuously (while (1)). Whenever I tried putting the functions in a loop, I kept on receiving the packets but not without this error: AXI DMA: RX error interrupts. The error is from the RxIntrHandler function. 

I ran the xaxidma_example_sg_intr.c and changed the code to run the sendpacket function in a loop and I could see the packets getting transmitted and received for the specified number of times.

After several attempts of changing the code, I am still unable to find the exact cause, could someone help me get rid of this error and receive the packets as they arrive.

Thank you.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
696 Views
Registered: ‎10-04-2016

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hi @bbhatt,

I'm not sure why cyclic mode would help you for the use case you describe. If you want to receive a buffer, modify it and then transmit that buffer, there's a lot of buffer descriptor management that has to happen. Cyclic mode seems like it would just complicate things.

You can use either DDR or BRAM--AXI DMA doesn't really care and the larger latency of DRAM isn't usually an issue. Typically there isn't sufficient BRAM in a device to support an Ethernet application so most customers use DRAM.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

11 Replies
Highlighted
Xilinx Employee
Xilinx Employee
957 Views
Registered: ‎10-04-2016

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hi @bbhatt,

You're going to need to dig into the code some more to figure out why you are hitting this error in order to know what to fix.

The error you are hitting occurs with the AXI DMA S2MM_DMASR register asserts the Err_Irq. Per PG021, the channel hit some non-specific error.

To get more detail into what happened, you need to look through the processed buffer descriptors to see where things went wrong. The field of interest is the S2MM_STATUS dword in the buffer descriptor. The obvious BD to start with is the one pointed to by the S2MM_CURDES registers--that's the descrptor that the AXI DMA Scatter Gather engine is processing. 

For details on the AXI DMA registers and buffer descriptor formats, refer to PG021.

https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
944 Views
Registered: ‎09-23-2018

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Thanks for the reply, I'll look into this and update the thread. 

0 Kudos
Highlighted
Contributor
Contributor
921 Views
Registered: ‎09-23-2018

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

I understand that this is something similar to what I require:https://forums.xilinx.com/t5/Networking-and-Connectivity/ZEDBOARD-RECEIVE-ETHERNET-PACKETS-INDEFINITELY/td-p/839418 but the solution is relevant for internal gigabit eth controller and I am using AXI ethernet, could you suggest an alternative for this. Thanks.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
854 Views
Registered: ‎10-04-2016

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hi @bbhatt ,

What you are wanting to do with the example code is not a trivial change. You are going to have to dive in and really understand how the AXI DMA bare metal driver works. 

The issue is in how you are post-processing and re-allocating the AXI DMA buffer descriptors. The bare metal AXI DMA driver documents its management of the BD ring here:

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.h

Perhaps running AXI DMA in cyclic mode would solve your problem. Please refer to PG021 to learn what cyclic mode is. There is a bare metal AXI DMA example that shows how to use this mode.

https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
845 Views
Registered: ‎09-23-2018

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Thank you for the reply. I'm aware about the cyclic mode and wanted to confirm if I can use it to receive packets continuously ? I understand that there are fixed no. of packets that can be received using this mode, kindly let me know if I've understood it correctly.

Thanks.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
833 Views
Registered: ‎10-04-2016

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hi @bbhatt,

Yes, you can use cyclic mode to re-use the same buffer descriptors continuously. This would be the equivalent of receiving packets continuously.

I do caution that folks tend to run into trouble in the post processing of the buffer descriptors in cyclic mode. The code has to be well tuned to make sure no packets are lost.

We actually just fixed a bug in the bare metal driver for 2019.1 because we weren't tracking completed descriptors properly.

https://github.com/Xilinx/embeddedsw/commit/79443aa1556f735e40acbc5fde9076d5671c960b#diff-ea35e0f75779e969f501e8ffe7c2937e

Regards,

Deanna

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
818 Views
Registered: ‎09-23-2018

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Thank you for the reply. I tried using the cyclic DMA code for receiving the ethernet packets, however, I end up getting the AXIDMA:Rx Error interrupts error. I have also modified the driver code as suggested previously. Could you please let me know if there is any step that is done incorrectly as the whole example is very difficult to understand and implement for the ethernet receive functionality.

 

 
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
805 Views
Registered: ‎10-04-2016

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hi @bbhatt ,

How far are you getting before you encounter the AXI DMA : RxError?

Going back to my original comment, you have to dig into the example code and PG021 to understand what is happening. Exactly which AXI DMA error you are getting on the receive channel? Without that, this is hard to debug--you can't sort it out just from code inspection. You need to instrument the receive interrupt handler to report the contents of the S2MM Status Register when you hit an error. There are more bits in that register that provide details about what error you have hit.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
734 Views
Registered: ‎09-23-2018

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution
Thanks for the reply. Could you let me know if cyclic mode is feasible to use if I want to receive packets, modify and transmit them using another port. Also, would it be advisable to use DDR or a BRAM should be used. Thanks
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
697 Views
Registered: ‎10-04-2016

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

Hi @bbhatt,

I'm not sure why cyclic mode would help you for the use case you describe. If you want to receive a buffer, modify it and then transmit that buffer, there's a lot of buffer descriptor management that has to happen. Cyclic mode seems like it would just complicate things.

You can use either DDR or BRAM--AXI DMA doesn't really care and the larger latency of DRAM isn't usually an issue. Typically there isn't sufficient BRAM in a device to support an Ethernet application so most customers use DRAM.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Highlighted
Visitor
Visitor
326 Views
Registered: ‎04-09-2019

Re: Regarding xaxiethernet_example_intr_sgdma example

Jump to solution

请问,如果想让pc ping这个千兆网口,我该怎么设置呢?

0 Kudos