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salettea
Visitor
Visitor
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Registered: ‎04-16-2019

Reset and stop core#1 on zynq7000

Hello,
I have a Zynq7000 and I am trying to hold in reset Core#1 as I am only using Core#2.
To do that, I used register F8000244 (A9_CPU_RST_CTRL) which can hold in reset and stop the core clock.
I managed to hold in reset Core#2 but when I am trying to stop the clock by activating. But the power consumption is slightly increasing (+35mW). Is it normal ? I was expecting to see the consumption decreasing.
There is more. When I try to stop the clock by using bit 5 of register F8000244, JTAG is shutting down, everything crashed and pop the following error :

salettea_0-1615821930550.png

Does somebody know how to shut down Core#1 when not used ? Is it possible the reduce power consumption by doing that ?
Regards

salettea_1-1615821962999.png

 

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derekm_
Voyager
Voyager
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Registered: ‎01-16-2019

Playing around with just the clocks/resets as you are doing is going to be unpredictable. In modern ASICs there is always a more defined way to reduce power in the system. Chapter 24 of the Zynq-7000 TRM (UG585) gives a lot of information on reducing power to various parts of the system (including putting one of the cores to sleep, I think). There is also some related material in the Arm A9 MPCore TRM.

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salettea
Visitor
Visitor
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Registered: ‎04-16-2019

Thank you for your answer.

Actually, playing with core reset is one of the ways I was expecting to reduce power. There are several other techniques that I implemented.

But I do not used Core#1 and I wanted to be sure that it was not consuming power. And the fact that stopping the clock makes the power consumption increase is confusing.

I did not find in those documentation where there is the explanation to put the core to sleep. Did you find it ?

Do you have any other ideas ?

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derekm_
Voyager
Voyager
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Registered: ‎01-16-2019

Pages 683 - 685 of UG585. (Apologies, no time to elaborate on anything else. Not much more to add anyway.)

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