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stonebull
Observer
Observer
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Registered: ‎07-10-2019

Route SDIO Interface through EMIO

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Hello,
I have a question regarding the SDIO interface of the Zynq7 Processing System.

I need to route it through EMIOs. But I do not need all the pins that are supplied. As you can see from the screenshot, in EMIO mode, the WP and CD pins are automatically included.

 

EnableSD0.PNG

 

 

 

 

 

 

 

 

So when making the Interface external, I get a load of unnecessary pins that now require a location and a level in the RTL's I/O Ports tab.

 

InstanceBlockDesign.PNG

 

 

I really just need the highlighted ones.

 

IOPorts.PNG

 

 


How do I prevent the other pins from been marked as "externals"?

If I don't assign them a location the Bitfile generation fails obviously. Some pins, at least the inputs, can be tied to HIGH or LOW internally, then they do not shine up in the I/O Ports tab, but what about the outputs, like "busvolt"?


Please help me! If you need any further information from me don`t hesitate from letting me know.

Best Regards,

Stone

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joseer
Voyager
Voyager
1,146 Views
Registered: ‎07-06-2016

Hi @stonebull ,  what I would do in that case (limited number of IO's) is to create a custom IP and manage/select all signals I want to route.  

I don't know if you've already seen it, but there's already a question about this topic where it is solved in this way:

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Leave-ports-unconnected-in-constraints-file/td-p/954017

Hope it helps.

Best regards.

View solution in original post

8 Replies
joseer
Voyager
Voyager
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Registered: ‎07-06-2016

Hi @stonebull ,

I'm having same issue, did you find out how to write the constrain file to route the SDIO signals through PL?

Thanks

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stonebull
Observer
Observer
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Registered: ‎07-10-2019

Hi joseer,

unfortunately not, I decided to change the design and use the MIO pins instead as a new HW revision was pending anyway. But I'd still would like to know if there is a solution to this.

Did you resolve the issue in the mean time?

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joseer
Voyager
Voyager
1,278 Views
Registered: ‎07-06-2016

Hi @stonebull ,

Yes, I found the way to write the constraints for them, the trick was to check how "xilinx" call them in the schematic after synthesis and then use those names, here's the SDIO constraints sample  I'm using in my design:

 

# SDIO EMIO

set_property PACKAGE_PIN F13 [get_ports SDIO_0_0_data_io[0]]
set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_data_io[0]]
set_property PACKAGE_PIN B14 [get_ports SDIO_0_0_data_io[1]] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_data_io[1]]
set_property PACKAGE_PIN A14 [get_ports SDIO_0_0_data_io[2]] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_data_io[2]]
set_property PACKAGE_PIN B13 [get_ports SDIO_0_0_data_io[3]] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_data_io[3]] set_property PACKAGE_PIN A13 [get_ports SDIO_0_0_cmd_io] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_cmd_io] set_property PACKAGE_PIN G13 [get_ports SDIO_0_0_cdn] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_cdn] set_property PACKAGE_PIN E14 [get_ports SDIO_0_0_clk_fb] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_clk_fb] set_property PACKAGE_PIN A12 [get_ports SDIO_0_0_clk] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_clk] set_property PACKAGE_PIN A11 [get_ports SDIO_0_0_busvolt[0]] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_busvolt[0]] set_property PACKAGE_PIN B11 [get_ports SDIO_0_0_busvolt[1]] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_busvolt[1]] set_property PACKAGE_PIN A10 [get_ports SDIO_0_0_busvolt[2]] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_busvolt[2]] set_property PACKAGE_PIN F12 [get_ports SDIO_0_0_led] set_property IOSTANDARD LVCMOS18 [get_ports SDIO_0_0_led]

But the problem I'm having now is that the SD card is not being detected by petalinux when is routed through EMIO but this is probably another different question to start in the forum (which probably won't get any answers like most of them).

Hope it helps others in future.

Best regards.

 

 

 

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stonebull
Observer
Observer
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Registered: ‎07-10-2019

Nice!

Thanks for posting your solution.

But how do you exclude some outputs from being synthisized? Can you set constraints to leave them unconnected?

Best regards

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joseer
Voyager
Voyager
1,263 Views
Registered: ‎07-06-2016

No worries, happy to help.

Well, I'm using all signals so I have not tried that, but I think that you could make external only the signals you want and having in consideration that  the SDIO are  in/out data and cmd lines, you would need some how to add IOBUF instances as it does vivado, i.e:

Untitled.jpg

I think that the easiest and simplest way is  to make the SDIO group external and use physically the ones you need.

Best regards.

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stonebull
Observer
Observer
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Registered: ‎07-10-2019

I agree, you could make all externals and use only those you need. Although given a case where you don't have spare pins that can be driven by e.g. the "busvolt" signals (which I don't need), is there a way to just ignore thoes outputs?

As far as I recall Vivado kept throwing an error whenever I tried to run Implementation with some outputs left unconnected to an external port.

Maybe there is some kind of "constant block" to add in block design which replaces a floating connection - or you could write your own ip core that has exactly this functionality. But it seems strange to me that xilinx does not offer anything for this purpose...

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joseer
Voyager
Voyager
1,147 Views
Registered: ‎07-06-2016

Hi @stonebull ,  what I would do in that case (limited number of IO's) is to create a custom IP and manage/select all signals I want to route.  

I don't know if you've already seen it, but there's already a question about this topic where it is solved in this way:

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Leave-ports-unconnected-in-constraints-file/td-p/954017

Hope it helps.

Best regards.

View solution in original post

stonebull
Observer
Observer
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Registered: ‎07-10-2019
Hi @joseer, thanks, that was kind of the solution that I had in mind too... good to know that it works, although kind of strange that there is no better way to do it.
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