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Participant
Participant
260 Views
Registered: ‎02-05-2020

S2MM DMA

Hello  Experts,

          I need support from you people for data transfer from PL to DDR memory, please do help because I am facing this problem from last one month.

My design is very simple, as show in timing diagram on every 5ms new 1K FFT data is computed, this data to be transfer to DDR memory continuously . 

DMA.JPG

For this, I am operating AXI DMA in Direct Register mode  and in S2MM mode only.

My C code written in such a way that, 

int main()
{
    init_platform();  // initialize the arm loading initial register value
    ps7_post_config(); // initialize the arm as per our requirement

    xil_printf ( " initializing AXI-DMA.........\n\r");
    InitializeAXIDMA();  // configuring S2MM.CR Register
while(1){
   xil_printf ( "Enabling The Interrupt Handling System............\n\r");
   InitializeInterruptSystem ( XPAR_PS7_SCUGIC_0_DEVICE_ID );

   Xil_DCacheFlushRange(XPAR_AXI_DMA_0_BASEADDR, 0xC00);

   // DDR memory Address and Length Declaration
   StartDMATransfer_DestinationAddress(DDRAddress);
   StartDMATransfer_Length(DDRLength);

   for (int i=0; i<1024; i++){
       	unsigned int tmpval;
       	tmpval = Xil_In32(DDRAddress+ (i*4));
       	xil_printf("= %x, %d \t\r", tmpval, i);
       }
   ClearInterrupt(); // clear interruput by writing 1 in 12th bit of S2MM.SR Register
}
    return 0;
}

For the above code, I am able to see only first frame data in DDR memory. Its not getting updated by other frame data.

After reading first frame I am clearing interrupt, to allow a second frame data to transfer in DDR.

Interrupt have cleared (i.e logic low) this I can monitor in debugger.

But S_AXI_S2MM_ready is not ready to accept new data ( its logic 0 always after transferring first frame).  

I think for this reason, it seems I am unable to transfer 2nd frame data and others also, so could anybody can help me to resolve this.

But when I reload .elf file on Zynq, I can see second frame data in DDR memory. For 3rd frame data to transfer on DDR I should reload .elf file once again.

Until I realod I 

The below code is interrupt mechanism code, Is it correct?. Because this code I have not understood. I have copied from internet source. this contain 3 function. the function InterruptHandeler() contain print statement "DMA Interrupt", when I do debug this statement I can not see in debugger window. this mean this function is not calling. 

void InterruptHandler(void){ // InterruptHandler To the Interrupt
   xil_printf("  DMA Interrupt");
    StartDMATransfer_DestinationAddress( DDRAddress);
    StartDMATransfer_Length(DDRLength);
}


int SetupInterruptSystem(XScuGic *XScuGicInstancePtr){
	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) XScuGic_InterruptHandler, XScuGicInstancePtr );
	Xil_ExceptionEnable();   //Enable Interrupt in ARM
	return XST_SUCCESS;
}


int InitializeInterruptSystem( InterruptDeviceID){

	 int Status;
	 /*
	  * Initialization functions in xscugic_sinit.c
	  */
	 GICConfig = XScuGic_LookupConfig(InterruptDeviceID); //Looks up the device configuration based on the unique device ID.
	     if(NULL == GICConfig) {
	    	 return XST_FAILURE;
	     }

	 Status = XScuGic_CfgInitialize ( &InterruptController, GICConfig, GICConfig->CpuBaseAddress);  //Initialize fields of the XScuGic structure and vector
	 	 if( Status != XST_SUCCESS) {
	 		 return XST_FAILURE;
	 	 }

	 Status = XScuGic_Connect ( &InterruptController, XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR, (Xil_ExceptionHandler)InterruptHandler, NULL); // Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.
 	 if( Status != XST_SUCCESS) {
 		 return XST_FAILURE;
 	 	 }

 	XScuGic_Enable ( &InterruptController, XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR);
 	return XST_SUCCESS;

}

Please do help I am facing this problem from last one month. If you want any other information, I would like to share.

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2 Replies
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Scholar
Scholar
233 Views
Registered: ‎05-21-2015

@desai_,

Have you thought through the consequences of restarting the DMA both at the normal software level and at the interrupt level?

Dan

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Participant
Participant
214 Views
Registered: ‎02-05-2020

I thought after every transition, reseting or clearing interrupt is required in DMA. So I am following the same in my design also

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