Dylan,
My name is Wen-Chun. I am working with Scott on solving this problem. We have come up with a possbile approach:
Build a custom IP that acts as a bus master, and design the state machine in the "user_logic.vhd" that controls the data transfer:
Processor <--> PLB <--> IP <-->dual port BRAM <--> other logics.
<--> MIC <--> SDRAM
The operation is: the "other logics" generates data and writes to the BRAM (in the fabrics). The IP monitors the BRAM rd/wr pointers
and read data from it, then pushes the data on to the PLB, enrouted to the memory-mapped off-chip SDRAM, all without the intervention
of the processor. The processor reads the data from the SDRAM when it needs to. (The BRAM rd/wr pointers are also
memory-mapped and available to the processor) . The IP can also read data from the SDRAM and write them to the BRAM.
The question for this approach is (1) Is the SDRAM accessible this way? We thought it is memory-mapped and the cross-bar should route
the data (2) from the user_logic.vhd generated by EDK for a bus-master test custom IP. It seems three parts are needed to perform data transfer betwwen
the IP and the PLB: is it correct ?
(a) a state machine controlling signals such as:
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Type <= mst_cmd_sm_xfer_type;
IP2Bus_Mst_Length <= mst_cmd_sm_xfer_length;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
(b) state machines for locallink interfaces that controls signals such as those:
IP2Bus_MstWr_src_rdy_n <= not(mst_llwr_sm_src_rdy);
IP2Bus_MstWr_src_dsc_n <= '1'; -- do not throttle data
IP2Bus_MstWr_rem <= (others => '0');
IP2Bus_MstWr_sof_n <= not(mst_llwr_sm_sof);
IP2Bus_MstWr_eof_n <= not(mst_llwr_sm_eof);
(c) a data FIFO that holds the data:
DATA_CAPTURE_FIFO_I : entity proc_common_v3_00_a.srl_fifo_f
generic map
(
C_DWIDTH => C_MST_DWIDTH,
C_DEPTH => 128
)
port map
(
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
FIFO_Write => mst_fifo_valid_write_xfer,
Data_In => Bus2IP_MstRd_d,
FIFO_Read => mst_fifo_valid_read_xfer,
Data_Out => IP2Bus_MstWr_d,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open
);
Thanks.
Wen-Chun
