SPI core simulation issue

[ryogitha]

Hi,

I have an axi_quad_spi core configured as a slave in design. The project is targeted for kintex 7 FPGA. and the configuration of the ip is as below. 

 

 I have same core configured as master in the testbench.

Through the AXI interface I have filled SPI DTR (Data transmit) FIFO and  the data is read back from the master SPI DRR (data receive) FIFO. 

It is observed that when DRR on master side is read, the first set of data that is written into DTR of SPI slave is read twice. Master has to generate extra clock cycles to read the last data.

This issue is seen only from slave DTR to master DRR (path highlighted in red). From master DTR to slave DRR the data is received accurately

I have set master in loopback mode and there is no repetition in the data received. Also the clock settings are same on both sides.

Can anyone help on this.

Thanks,

Yogitha

[smarell]

I'm unable to reproduce this issue at my end. I sent you the example archive via FTP. Please test it at your end and provide me an update.

[ryogitha]

@smarell,

Can you please share the FTP link.

Thanks,

Yogitha

[ryogitha]

Hi @smarell,

I would like to add one more thing here. This data repetition is observed only from the second transaction. For the first transaction, data is read accurately on both sides. We found this data repetition in example design as well

Thanks,

Yogitha

[smarell]

I'll modify the example design for performing two transactions. Please feel free to share your test case via FTP link if you are seeing the issue only with specific commands.

[ryogitha]

Hi @smarell,

I have created example design for below configuration of axi_qspi ip in slave mode and updated coefficient files of the trafiic gen ip in example design to enable second transaction.

Data repetition is seen in the second transaction

.I have attached the updated coefficient files. May be you can use these files to run simulation of example design from your end.

Also I found this old forums post on similar issue https://forums.xilinx.com/t5/Welcome-Join/Axi-Quad-SPI-slave-8-bit-problem/td-p/760925 and the work around suggested there did work in simulation.

Can you please help on this and confirm if this is a bug or design issue and also suggest a work around.

Thanks,

Yogitha

[smarell]

I was unable to reproduce the issue that you stated post updating the ATG coe files with the ones you shared in 2018.2 AXI Quad SPI IP example design. I shared the project archive with you via EzMove.

I also analysed the IP source files and couldn't find any issue with the code that can result in the issue that you stated.

[ryogitha]

@smarell,

I did receive the project archive link through EZmove but did not receive any notification regarding the login credentials. Xilinx userid doesn't seem to work here. Can you please check on this.

Mean while I did try the same project in vivado 18.2 and still see the same issue. Just to confirm, are you also monitoring the read data bus from master spi?

As mentioned earlier, master_write to slave_read  is working properly. Slave_DTR to master_DRR has the data repetition issue.

Thanks,

Yogitha

[smarell]

Please use your current email and click on reset password. Then you can set your password and will be able to login to ezmove.

Yes I've tested the scenario that you mentioned and didn't see any issue.

[ryogitha]

@smarell,

 I followed the link in the email to the sign in page of ezmove. I did try to reset the password, but I need to give user name to get email notification. I tried with Xilinx user name but I did not get any response at my registered email. 

I have got another question, Why do I not get email notification when someone replies on this post. I am sure there must be some settings for this. I did try to find this but no luck. Can you help me with this. This will save my time and help to respond quickly as this is at critical stage of our project.

Thanks,

Yogitha

[smarell]

@ryogitha You should provide your registered email address in username. In the interest of time, I can schedule a WebEx session tomorrow to investigate this issue. Please suggest a convenient time for the same.

[ryogitha]

@smarell,

I was able to access the example design you shared. I ran simulation and found the same issue there. On master read channel I see data 00000008 repeated twice.

Below fig is spi slave s_axi4_wdata to fill DTR for second transaction

spi slave write

As you can see in below figure s_axi4_rdata of master spi reads first data 00000008 twice.

spi master read

For webex any time after 3 pm IST is fine.

Thanks,

Yogitha