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Visitor
Visitor
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Registered: ‎07-23-2018

SPI0-MIO Configuration in Zynq 7000 (XC7Z020) device- SPI lower speed configuration

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Hi,

I have configured SPI0 of XC7Z020 as MIO, and the requested frequency for SPI in IO peripheral configuration tab of clock configuration = 125 Mhz.

Input Frequency = 33.33 MHz

CPU Clock ratio = 6:2:1

CPU Clock = 666.66 MHz

SPI_1.png

When I tried changing the frequency to 50Mhz , It throws the error message :

"Validation failed for parameter 'PCW SPI PERIPHERAL FREQMHZ(PCW_SPI_PERIPHERAL_FREQMHZ)' with value '50' for BD Cell 'Processor/processing_system7_0'. SPI frequency 50.000000 (MHz) should be greater than CPU_1x 111.111115 (MHz). Please select the correct SPI frequency again"

SPI_12.png

But as per the document Zynq 7000 SoC technical reference Manual,UG585(Link: https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) Section 17.1.1

explains the Features of SPI controller:

"50MHz SCLK clock frequency when I/O signals are routed to the MIO pins" 

  1. Kindly help in understanding how it works.
  2. Why am I unable to change the SPI clock below the CPU clock frequnecy.
  3. If I need a lower SPI clock frequency how do we configure it

Thanks in Advance.

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Xilinx Employee
Xilinx Employee
622 Views
Registered: ‎09-01-2014

Re: SPI0-MIO Configuration in Zynq 7000 (XC7Z020) device- SPI lower speed configuration

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The clock you are setting in PCW is a reference clock, not SCLK.
Please check 17.4.2 Clocks section of UG585

SCLK is generated by a reference clock with the baud rate divider.

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Xilinx Employee
Xilinx Employee
623 Views
Registered: ‎09-01-2014

Re: SPI0-MIO Configuration in Zynq 7000 (XC7Z020) device- SPI lower speed configuration

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The clock you are setting in PCW is a reference clock, not SCLK.
Please check 17.4.2 Clocks section of UG585

SCLK is generated by a reference clock with the baud rate divider.

View solution in original post