05-07-2010 02:29 AM
I have a qustion about the SRAM on ML507 FPGA board.
I am trying to access SRAM in EDK through the MCH EMC interface. It seems the MCH EMC interface can be configured working at 200MHz. My problem is, my own custom IP is working at 200MHz and needs to read data from SRAM every other clk periods. However, I can see from ChipScope that there is a great latecy between sending address from my ip to receiving the needed data from SRAM, that is about 10 clk periods. Does anyone have any idea about this problem? Is it the face that there indeed has such a great latency when comes to reading from SRAM, or, maybe i have made some mistakes that lead to this serious problem.
I find it saying that the ZBT SRAM can get the data two clk cycles after the address in the following document.
It is talking about another kind of SRAM or it is the very SRAM on ML507 FPGA board?
I am really confused about this. Can anybody give me some ideas? Many manythanks...
08-24-2010 07:05 PM
hello ,i am focus on the simulation about the zbt sram contrller using the XAPP136 under the XUP-LX110T,but ,i find that ,i can't write and read date through the controller,is any on can tell me the solution,thanks.