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Visitor
Visitor
3,612 Views
Registered: ‎05-05-2010

SRAM on ML507 FPGA board

Hi everyone,

 

I have a qustion about the SRAM on ML507 FPGA board.

I am trying to access SRAM in EDK through the MCH EMC interface. It seems the MCH EMC interface can be configured working at 200MHz. My problem is, my own custom IP is working at 200MHz and needs to read data from SRAM every other clk periods. However, I can see from ChipScope that there is a great latecy between sending address from my ip to receiving the needed data from SRAM, that is about 10 clk periods. Does anyone have any idea about this problem? Is it the face that there indeed has such a great latency when comes to reading from SRAM, or, maybe i have made some mistakes that lead to this serious problem.

I find it saying that the ZBT SRAM can get the data two clk cycles after the address in the following document.

http://www.xilinx.com/support/documentation/application_notes/xapp136.pdf

It is talking about another kind of SRAM or it is the very SRAM on ML507 FPGA board?

I am really confused about this. Can anybody give me some ideas? Many manythanks...

 

Hao

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Visitor
Visitor
3,487 Views
Registered: ‎11-05-2008

hello ,i am focus on the simulation about the zbt sram contrller using the XAPP136 under the XUP-LX110T,but ,i find that ,i can't write and read date through the controller,is any on can tell me the solution,thanks.

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Xilinx Employee
Xilinx Employee
3,430 Views
Registered: ‎08-01-2007

Are you seeing the sending address from PLB BUS or EMC core interface?

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