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Observer
Observer
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Registered: ‎03-14-2018

Save serial ADC input to DDR using DMA on Zedboard

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Hi 

I am trying to save ADC data (the ADC IC is LTC1403A) that is coming in at MIO JA1 of the Zedboard to DDR using DMA. I am generating in an IP tvalid and tlast according to the LTC1403A DS.

However where I am still confused with is, do I have to parallelize the data before trying to send it to AXI DMA? How would that then work with tvalid and tlast?

Thanks for any help.

Best Regards

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691 Views
Registered: ‎06-21-2017

Re: Save serial ADC input to DDR using DMA on Zedboard

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Yes, convert your data to parallel.  I also suggest sign extending it to 16 bits.  You will probably want to write the data 2 samples at a time to an AXI stream FIFO.  I say this because I think the smallest DMA bit width is 32 bits, but I'm only familiar with Ultrascale.  You will want to pass a fixed number of words at a time.  Let's call it 256 words or 512 samples.    tvalid will be your FIFO write signal.  Every 256 words, assert tlast to your FIFO.  The other end of the FIFO is attached to an AXI DMA controller.  When the DMA controller sees tlast out of the FIFO, it can generate an interrupt, telling the software that there is another block of data to process.  Read PG201, the AXI DMA Controller product guide.  Work through the Zedboard DMA examples.  Don't get too frustrated.  It will take a while to absorb all of this.

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Registered: ‎06-21-2017

Re: Save serial ADC input to DDR using DMA on Zedboard

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Yes, convert your data to parallel.  I also suggest sign extending it to 16 bits.  You will probably want to write the data 2 samples at a time to an AXI stream FIFO.  I say this because I think the smallest DMA bit width is 32 bits, but I'm only familiar with Ultrascale.  You will want to pass a fixed number of words at a time.  Let's call it 256 words or 512 samples.    tvalid will be your FIFO write signal.  Every 256 words, assert tlast to your FIFO.  The other end of the FIFO is attached to an AXI DMA controller.  When the DMA controller sees tlast out of the FIFO, it can generate an interrupt, telling the software that there is another block of data to process.  Read PG201, the AXI DMA Controller product guide.  Work through the Zedboard DMA examples.  Don't get too frustrated.  It will take a while to absorb all of this.

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Observer
Observer
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Registered: ‎03-14-2018

Re: Save serial ADC input to DDR using DMA on Zedboard

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Thanks @bruce_karaffa this makes it much clearer.

I am trying to send 16 bits at a time, but can double it to 32.

However I was having tvalid high during the serial stream of the 16 bits and tlast coming at the end of the 16 bits. I guess that is wrong.

Following your email I have to "packetize"  16 (or 32) bits to parallel "bursts" and keep on sending them out while tvalid stays high and after 256 packets have a tlast pulse and pull tvalid down.

Is there any method or code you would suggest for parallelizing the data?

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Mentor
Mentor
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Registered: ‎02-24-2014

Re: Save serial ADC input to DDR using DMA on Zedboard

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Run the IO wizard in the IP catalog, and it will generate a serial to parallel interface for you..    That code will need some modification to synchronize the words properly.   There are lots of methods to do that.

Don't forget to close a thread when possible by accepting a post as a solution.
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Observer
Observer
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Registered: ‎03-14-2018

Re: Save serial ADC input to DDR using DMA on Zedboard

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Thanks @jmcclusk and @bruce_karaffa for the help. 

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