08-18-2020 04:07 AM
How can I ensure that each time I write a data from PS to PL through Xil_Out command I latch it at the clock edge? and what if I want to write to a register through Xil_Out and read from another one through Xil_In at the same time?
08-18-2020 05:03 AM
Hi @dinaemadeldin ,
You can write into a register and after that you can check it immediately after.
But you need to know communication between PS & PL is also related with features of related address blocks.
When you configure your address block differently you can see different results, because of sharing and caching properties.
It changes also read/write speeds.
I can share my previous post about that. I lived a speed problem about PS to PL and vice versa.
I solved it by changing features of related address range.
Saban
08-18-2020 05:03 AM
Hi @dinaemadeldin ,
You can write into a register and after that you can check it immediately after.
But you need to know communication between PS & PL is also related with features of related address blocks.
When you configure your address block differently you can see different results, because of sharing and caching properties.
It changes also read/write speeds.
I can share my previous post about that. I lived a speed problem about PS to PL and vice versa.
I solved it by changing features of related address range.
Saban