07-21-2016 09:07 AM
I need to move some amount of data packets to the DDR3 memory of my ZC702 evaluation kit. The problem appears if this data is not aligned, I mean the packet number 2 doesn't go next to packet 1 or packet 3, it can goes to other position in the DDR3. This position change is generated by a vhdl module that I have created and it works well. I have uploaded a picture for better understanding the situation.
At the moment I have written one VHDL module with AXI4-Lite interface (I have chosen that option because I can't use the burst of the AXI4 specification) which is connected to the AXI4 memory map. It works but it generates some glitches in the DDR3 final data (Corruption of some data and also misalignment problems).
My question is: can I use a IP core for doing transfers but not as they have used typically because I need to change the address for each transaction? How can do that? Any idea about why my AXI4-Lite module is generating some glitches?
Thank you very much!
07-31-2016 11:01 AM
08-08-2016 05:08 AM
08-29-2016 09:41 PM
I use BRAM for this purpose:
Here's my process in my blockmem_tester_v1_0 IP:
variable addr : integer := 0;
if rising_edge(CLK) then
addra <= std_logic_vector(to_unsigned(addr, 32));
dina <= x"efbeadde";
addr := addr + 4;
if addr = 8192 then
addr := 0;
ena <= '1';
wea <= "1111";
In address editor my axi_bram_ctrl_0 starts at address 0x40000000 with an 8KB range. On the PS side I use /dev/mem in Linux:
int m = open("/dev/mem", O_RDWR | O_SYNC); unsigned long* addr = mmap(NULL, 8192, PROT_READ | PROT_WRITE, MAP_SHARED, m, 0x40000000);
I can now read/write to *addr.
Hope this helps. Took me a long time to achieve this so I hope it provides a short cut for some.