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lluisrovirale
Visitor
Visitor
5,295 Views
Registered: ‎05-06-2015

Sending data from PL to DDR3 without using stream/burst

Hi,

I need to move some amount of data packets to the DDR3 memory of my ZC702 evaluation kit. The problem appears if this data is not aligned, I mean the packet number 2 doesn't go next to packet 1 or packet 3, it can goes to other position in the DDR3. This position change is generated by a vhdl module that I have created and it works well. I have uploaded a picture for better understanding the situation.

 

xilinx_forum.png


At the moment I have written one VHDL module with AXI4-Lite interface (I have chosen that option because I can't use the burst of the AXI4 specification) which is connected to the AXI4 memory map. It works but it generates some glitches in the DDR3 final data (Corruption of some data and also misalignment problems).

My question is: can I use a IP core for doing transfers but not as they have used typically because I need to change the address for each transaction? How can do that? Any idea about why my AXI4-Lite module is generating some glitches?

 

Thank you very much!

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smarell
Community Manager
Community Manager
4,928 Views
Registered: ‎07-23-2012

You can try AXI DMA or AXI Data mover for this purpose.
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muzaffer
Teacher
Teacher
4,641 Views
Registered: ‎03-31-2012

why can't you use burst? coding a master with burst capability is easy. In your list of options, you can use the first and third. Or you can code an axi master in C and use HLS.

Your problems about data corruption can be due to caching. When you write to memory through HPx ports, the processor doesn't know that the memory has changed. You need to manage cache properly.
Another option is to connect your master to ACP and set ACP to coherent mode. This might get rid of the glitches if caching is your problem.
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neilking
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Registered: ‎08-29-2016

I use BRAM for this purpose:

 

Selection_001.png

 

Here's my process in my blockmem_tester_v1_0 IP:

 

process(CLK)

variable addr : integer := 0;

begin

if rising_edge(CLK) then

addra <= std_logic_vector(to_unsigned(addr, 32));
dina <= x"efbeadde";
addr := addr + 4;
if addr = 8192 then
addr := 0;
end if;
ena <= '1';
wea <= "1111";

end if;
end process;

In address editor my axi_bram_ctrl_0 starts at address 0x40000000 with an 8KB range.  On the PS side I use /dev/mem in Linux:

 

int m = open("/dev/mem", O_RDWR | O_SYNC);
unsigned long* addr = mmap(NULL, 8192, PROT_READ | PROT_WRITE, MAP_SHARED, m, 0x40000000);

I can now read/write to *addr.

 

Hope this helps.  Took me a long time to achieve this so I hope it provides a short cut for some.

 

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