11-17-2017 02:38 AM
This is regarding picoZed board/ Zynq 7030 with FMC Carrier card and the associated Serial Rapid IO (SRIO) example in Xilinx SDK 2016.4.
I want to run a Serial Rapid IO example named 'xsrio_dam_loopback_example' that I picked from board support package (BSP). the system.mss file in BSP lists srio_gen2_0 module and this example. The code loads and the execution starts fine, until it halts at
/* Set the Water Mark Level to transfer priority 0,1,2 packet */
XSrio_SetWaterMark(InstancePtr, 0x5, 0x4, 0x3);
with error of Xil_DataAbortHandler. could you please help.
11-17-2017 04:52 AM
I found out that my address space for SRIO module address range is 0x60000000 to 0x6000FFFF. and the offset in this command is at 0x10000. This is why the code hangs at the function call of XSrio_SetWaterMark. is there meant to be minimum SRIO module range?
11-20-2017 01:44 AM
Refer from page 86 of below doc
upper 8 bits are for hop count and lower 24 bits are the configuration offsets out of the 32 bit address.
So to access the local end point address bits [31:24] should be zero
As 0x00000000 to 0x40000000 address space is allocated for DRAM and OCM
You can use slice and concate blocks to drive the upper 8 bits connected to the axi4 lite interface of the core to zero's to access the maintenance writes and reads.
11-20-2017 04:36 AM
We have catered for this in the following way. We use the upper 4 address bits for the decode for the SRIO Maintenance write and reads. We only use 4 hop bits (bits 24 to 27) as there are not many hops required in the system. The upper 4 address bits are forced to 0000 before being presented to the Maintenance port.
I want to achieve internal loopback using the example code, the TX buffer is in DDR memory which I see in 'memory monitor' window. Next I want SRIO to drop the received buffer in DDR or SRIO's own memory space. the example code runs to the end but I do not see the received data as expected.
11-28-2017 09:05 AM
We went further than abovementioned issue and would appreciate if someone can help us.
The SRIO example uses AXI_DMA to make a transfer. The SRIO code runs fine until it stays on the following line
/* Wait till S2MM Transfer Complete */ while(!( XAxiDma_ReadReg(DmaConfig->BaseAddr, XAXIDMA_RX_OFFSET+XAXIDMA_SR_OFFSET) & 0x1000));
I have successfully tested AXI_DMA standalone with its own examples but when linked to SRIO, it does not read the transfer completion register. The view of AXI DMA in memory view window and in Expressions window is as follows. Could you please tell if any of the settings are wrong for this SRIO DMA transfer? The MEM_ADDR is DDR base address. This is where SRIO Hello world message lies.
#define MEM_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR//0x00100000