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c.dinh
Observer
Observer
6,162 Views
Registered: ‎06-19-2014

Shared AXI ressources between PS FPD and PS LPD through the M_AXI_HPM0_LPD port ?

Hello,

 

I have implemented an AXI bus with different ressources in the PL. This design comes from a previous project based on a ZYNQ 7000 MPSOC where these ressources were shared by both of the CPUs, one running on LINUX and the other one running on a freeRTOS, and it was working fine.

 

Now I'm porting this design on a ZYNQ Ultrascale+ and I have attached these AXI ressources on the M_AXI_HPM0_LPD interface. My RPU access correclty to it, but I'm unable to access it through the APU.

 

Reading the TRM, chapter 35, figure 35.1, I don't see any "clear" path to access to the M_AXI_HPM0_LPD from the APU, except maybe through the CCI400 then the Core Switch then the RPU core switch then the M_AXI_HPM0_LPD...And page 953 it is written "IMPORTANT : Exclusive access by the APU cannot be made to the M_AXI_HPM0_LPD signal due to an ID
converter in the path", what does it mean?

 

So my question is simple : is it possible for the APU to access to the M_AXI_HPM0_LPD?

 

Regards, Christophe

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7 Replies
pvenugo
Moderator
Moderator
6,112 Views
Registered: ‎07-31-2012

Hi,

 

As block diagram and explanation says  M_AXI_HPM0_LPD cannot be accessed by APU.

Instead can you use _FPD interface port?

 

Regards

Praveen


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c.dinh
Observer
Observer
6,099 Views
Registered: ‎06-19-2014

Thank you for your response, I wasn't sure reading the docs, now I am sure! As you propose, I'll implement an AXI on the _FPD port.

 

Regards, Christophe

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ariefgrand
Observer
Observer
4,891 Views
Registered: ‎03-03-2015

Hello,

Did you succeed in doing this?
I have a similar problem. I want to migrate my design from Zynq-7000 to Ultrascale+.
For me, I'm not sure which port do I have to use, FPD or LPD? Could you give me some direction?
Thank you.

Regards,
Arief
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pvenugo
Moderator
Moderator
4,870 Views
Registered: ‎07-31-2012

Hi @ariefgrand,

 

Please give me details of the existing Zynq7000 design which you want to migrate to ZU+.

 

Regards

Praveen


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ariefgrand
Observer
Observer
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Registered: ‎03-03-2015

Hi @pvenugo,

 

Thank you for your reply.

I have an IP that uses an AXI-Lite slave interface and an AXI-Full master interface.

The ARM processor will send a configuration and let the IP write/read via DMA using the AXI-Full master interface.

I have some problems which did not exist when I used Zynq-7000.

For example, I found that after the FPGA configuration, I cannot access the AXI slave directly in the same script.

I have to separate the configuration and the access to AXI into two scripts and execute them one after another.

Are you aware of this problem?

There are some other problems but I think it should be posted in other topics of thread.

 

Thank you so much for your help.

 

Best regards,

Arief

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mnanoop2014
Participant
Participant
3,272 Views
Registered: ‎10-29-2018

@ariefgrand Can you kindly disambiguate what you mean by configuration and also two scripts? I'm new to this terminology and am facing similar problems

 

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cch
Xilinx Employee
Xilinx Employee
1,270 Views
Registered: ‎09-04-2012

Christophe,

Yes, the APU can access the HPM0_LPD port using the 512MB address space starting at 0x8000_0000.

Exclusive access means load or store exclusive instructions (LDXR/STXR).

Regards,

Christophe

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