03-23-2017 04:02 AM
I have implemented an AXI bus with different ressources in the PL. This design comes from a previous project based on a ZYNQ 7000 MPSOC where these ressources were shared by both of the CPUs, one running on LINUX and the other one running on a freeRTOS, and it was working fine.
Now I'm porting this design on a ZYNQ Ultrascale+ and I have attached these AXI ressources on the M_AXI_HPM0_LPD interface. My RPU access correclty to it, but I'm unable to access it through the APU.
Reading the TRM, chapter 35, figure 35.1, I don't see any "clear" path to access to the M_AXI_HPM0_LPD from the APU, except maybe through the CCI400 then the Core Switch then the RPU core switch then the M_AXI_HPM0_LPD...And page 953 it is written "IMPORTANT : Exclusive access by the APU cannot be made to the M_AXI_HPM0_LPD signal due to an ID
converter in the path", what does it mean?
So my question is simple : is it possible for the APU to access to the M_AXI_HPM0_LPD?
03-26-2017 03:41 AM
As block diagram and explanation says M_AXI_HPM0_LPD cannot be accessed by APU.
Instead can you use _FPD interface port?
03-27-2017 02:16 AM
Thank you for your response, I wasn't sure reading the docs, now I am sure! As you propose, I'll implement an AXI on the _FPD port.
12-06-2017 02:16 AM
12-07-2017 09:57 PM
Please give me details of the existing Zynq7000 design which you want to migrate to ZU+.
12-08-2017 10:08 AM
Thank you for your reply.
I have an IP that uses an AXI-Lite slave interface and an AXI-Full master interface.
The ARM processor will send a configuration and let the IP write/read via DMA using the AXI-Full master interface.
I have some problems which did not exist when I used Zynq-7000.
For example, I found that after the FPGA configuration, I cannot access the AXI slave directly in the same script.
I have to separate the configuration and the access to AXI into two scripts and execute them one after another.
Are you aware of this problem?
There are some other problems but I think it should be posted in other topics of thread.
Thank you so much for your help.
01-21-2019 08:52 PM
06-22-2020 09:18 AM
Yes, the APU can access the HPM0_LPD port using the 512MB address space starting at 0x8000_0000.
Exclusive access means load or store exclusive instructions (LDXR/STXR).