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Registered: ‎03-19-2020

Simulate a complex custom IPs

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Hello to all the community,

I am currently developing such complex IPs to be integrated in design which has the aim of delivering the image processing based on new policies, and I want to test my IPs one by one, and passing by simulation, so is there any technics to handle this procedure?

 

Thanks for your advanced answers,

Tarek

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Scholar
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Registered: ‎05-21-2015

Re: Simulate a complex custom IPs

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@tarek_elouaret3,

SymbiYosys is useful for verifying IP cores.  While it has a limited simulation ability, it's not a tool I would recommend for simulation.  The problem with simulation is that you can only simulate situations you can imagine ahead of time.  Formal verification, separate from simulation, is valuable because when using it you can check for situations you haven't thought of in your test script.  Rather than following a test script, the formal engine checks *every* possible path through your logic to find one path, any path, causing it to violate a property you give it.

If you haven't heard of formal methods before, you can read about my own first experiences with formal verification here.  Just to try out the tool, I tested it on one of my FIFOs.  Let's just say that my pride was knocked down a notch in the process.

As far as I can tell, Xilinx's cores have been internally tested with simulation and cover checks, never formal methods. They generate simulation scripts internally to check their own cores, and then continue working on those scripts until each script checks every piece of logic within the core it is used to test.  I recently wrote about all the bugs I'd found using formal methods in Xilinx's IP cores earlier this year.  My point is, while this approach creates a nice feel good, they left some nasty bugs behind.  (Reading and writing to the ethernet core would send the write data to the read address?)

Feel free to dig some more.

If you want a simulator, Vivado comes with a nice simulation capability.  There's also open source simulation capabilities as well that will tend to be (less) capable.  ghdl, for example, works nicely for verifying VHDL designs.  I use Verilator almost exclusively for my own simulation needs.  Unlike Vivado's internal simulator, neither of these open source simulators are multi-lingual.  So, there's something to be said for knowing your options, and carefully choosing the best from among them.

Dan

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Re: Simulate a complex custom IPs

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Dependent on the interfaces of your IPs, the first thing that comes to my mind is the AXI VIP cores. Refer to PG267 PG291, PG298, DS941, DS940 & PG277. The VIP cores support AXILite, AXI4, AXIStream, AXI3, MPSOC, zynq7 PS, resets and clks. The neat part about the VIP cores is that they can be inserted into your design and act as a pass-through connection. During synthesis, the VIP becomes a bunch of wires. During sim, the test bench can access the VIP and react as a slave and/or master of the pass-through connection.

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Registered: ‎03-19-2020

Re: Simulate a complex custom IPs

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HI  @johnmcd ,

Thanks for your reply, I see that IP VIP has some advanced privilege, and that what came to my mind as the first solution, but I think that those IPs (VIP type) are coded only with Verilog, so it can be interfaced with custom IP based on VHDL?

In addition, my custom IP has AXI_lite interface, and some AXI stream master & slave

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Registered: ‎05-21-2015

Re: Simulate a complex custom IPs

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@tarek_elouaret3,

You should be aware that it's rather difficult to get an AXI interface right.  Xilinx didn't get their AXI-lite slave example (IP packager) interface right, nor did they get their example AXI interface right.  They've been broken since at least Vivado 2016.3--the earliest version I tested.

These are non-trivial bugs.  Although they aren't often triggered, when they are triggered the design in question will suddenly freeze and freeze hard.

You should also know that these example designs passed Xilinx's AXI VIP tests.

The bugs were found with a formal verification check, so I might argue that if you want to know if your design is bus compliant, then you really need to formally verify your design.  SymbiYosys is the tool I've used for that so far.  Verilog support is free and open source.  If you contact them, you may be able to get a trial version of VHDL support.

Dan

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Registered: ‎03-19-2020

Re: Simulate a complex custom IPs

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HI @dgisselq

Interesting explanation, very delighted to hear all of that, I will try to dig in more in this procedures and check out for this tool 'SymbiYosysso', so according to you, It might be useful to simulate and verify some complex custom IPs (whether it is written in Verilog or VHDL)?

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Xilinx Employee
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Registered: ‎02-01-2008

Re: Simulate a complex custom IPs

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Verilog has the capability to access buried entities when simulating. For example, a verilog testbench can access a clock within an instantiated block that does not bring the clock out. The VIP cores rely in this capability to kick off reads, writes, etc. But the VIP core can easily work with lower level vhdl logic.

In a recent design I worked with, the original developer preferred vhdl. So the simulation stackup was as follows:

  • his vhdl logic included an instantiation of a verilog wrapper testbench that contained the VIP calls
  • The verilog wrapper instantiated the verilog wrapper from IPI
  • The IPI block included the VIPs and various VHDL and Verilog IP blocks

So the verilog wrapper testbench contains calls such as:

design_1_wrapper_i.design_1_i.processing_system7_0.inst.set_slave_profile("S_AXI_HP0", 2'b00);

where the 'processing_system7_0.inst' represents one of the VIP cores (in this case for the zynq7 PS).

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Registered: ‎05-21-2015

Re: Simulate a complex custom IPs

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@tarek_elouaret3,

SymbiYosys is useful for verifying IP cores.  While it has a limited simulation ability, it's not a tool I would recommend for simulation.  The problem with simulation is that you can only simulate situations you can imagine ahead of time.  Formal verification, separate from simulation, is valuable because when using it you can check for situations you haven't thought of in your test script.  Rather than following a test script, the formal engine checks *every* possible path through your logic to find one path, any path, causing it to violate a property you give it.

If you haven't heard of formal methods before, you can read about my own first experiences with formal verification here.  Just to try out the tool, I tested it on one of my FIFOs.  Let's just say that my pride was knocked down a notch in the process.

As far as I can tell, Xilinx's cores have been internally tested with simulation and cover checks, never formal methods. They generate simulation scripts internally to check their own cores, and then continue working on those scripts until each script checks every piece of logic within the core it is used to test.  I recently wrote about all the bugs I'd found using formal methods in Xilinx's IP cores earlier this year.  My point is, while this approach creates a nice feel good, they left some nasty bugs behind.  (Reading and writing to the ethernet core would send the write data to the read address?)

Feel free to dig some more.

If you want a simulator, Vivado comes with a nice simulation capability.  There's also open source simulation capabilities as well that will tend to be (less) capable.  ghdl, for example, works nicely for verifying VHDL designs.  I use Verilator almost exclusively for my own simulation needs.  Unlike Vivado's internal simulator, neither of these open source simulators are multi-lingual.  So, there's something to be said for knowing your options, and carefully choosing the best from among them.

Dan

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Registered: ‎03-19-2020

Re: Simulate a complex custom IPs

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@dgisselq 

 

It's very clear of all what you said sir, I am really learning and enjoying for what you explained for this issue, the attribution of the test script simulation is based on the application developed, I will try to check out all shared links, and understand the formel verification, in order to get forward on this project, besides, may I have your contact on Linkedin to keep in touch with you in future or for other some expected questions.

Thanks in advance,

 

Tarek

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Registered: ‎05-21-2015

Re: Simulate a complex custom IPs

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@tarek_elouaret3,

I'm ...  not on linked in.  You can find my contact information at the bottom of any of the links I've cited above.

Dan

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Registered: ‎03-19-2020

Re: Simulate a complex custom IPs

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Thanks sir : ), done
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