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Registered: ‎08-07-2014

Slave AXI VIP read transaction logging/value returned


I'm working on a custom module in Verilog that will only generate AXI (full) read transactions towards a ZynqMP system with 2Gb RAM. For that, I'm

using AXI VIP as slave with memory model. My custom module just have the AXI read channels (Address read, Data+RRESP read).  It is connected

to the Slave AXI VIP through an AXI Interconnect. Here goes my entire block design:





AXI VIP is initialized as (based on Xilinx's AXI VIP as slave Wiki page):

axi4read_bd_axi_vip_0_0_slv_mem_t      slv_mem_agent;

    initial begin
        //Create an agent
        slv_mem_agent = new("VIP Memory",DUT.axi4read_bd_i.axi_vip_0.inst.IF);
        // set tag for agents for easy debug
        // set print out verbosity level.
        //Start the agent

"axi_vip_0" S_AXI is mapped to offset 0x0 range 2GB in address editor tab, just like the 'real memory'.

Well... VIP is initialized and return a value from the AXI Read transaction (testbench generates three reads):

XilinxAXIVIP: Found at Path: axi4read_tb.DUT.axi4read_bd_i.axi_vip_0.inst
[155 ns] Reset Deasserted
INFO: [DDR_Memory_wr_driver] (.axi_vip_v1_0_2_pkg.axi_slv_wr_driver(C_AXI_ADDR_WIDTH=64,C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=1,C_AXI_RID_WIDTH=1,C_AXI_HAS_BURST=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0,C_AXI_HAS_WSTRB=0,C_AXI_HAS_BRESP=0)::run_phase.Block12250_588.) 165 ns : run()
INFO: [DDR_Memory_monitor] (.axi_vip_v1_0_2_pkg.axi_monitor(C_AXI_ADDR_WIDTH=64,C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=1,C_AXI_RID_WIDTH=1,C_AXI_HAS_BURST=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_CACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=0,C_AXI_HAS_QOS=0,C_AXI_HAS_WSTRB=0,C_AXI_HAS_BRESP=0)::run_phase.Block8397_572.) 165 ns : run()
[336 ns] Value read = 0x10642120c03b2280
[626 ns] Value read = 0x10642120c03b2280
[916 ns] Value read = 0x10642120c03b2280

My question is: Is it possible to generate a log with details about the read transaction, just like happens when we do a *write* using AXI VIP as master?

I'd like to make sure my module is really working.

Does VIP in memory model always return the above value? Does it seems correct? I've tried different addresses and return are the same.

BTW, RRESP is 0 when the read data is available, which is good :)


Thanks in advance for any clarification!


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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Hi @brasilino ,

The AXI VIP in slave memory mode will generate random read data when the location hasn't been previously written. I am not sure if the random data always uses the same seed or not.

You could use the backdoor_memory_write API to condition the AXI VIP slave memory with know values. That way you would have a way of tracking whether the AXI VIP is returning the expected data to your master IP.



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