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Adventurer
Adventurer
482 Views
Registered: ‎05-18-2018

SmartConnect configuration problem / AXI master tie-off

I am using vivado 2019.1 and an UltraScale+ SoC.

I am using a Video Mixer block configured for 3 overlay layers. Configuring for overlay layers creates an AXI master output on the Video Mixer block for each such layer.

At the beginning, I ignored the AXI master outs on this block, but design validation threw some warnings, so I ran the AXI masters to a SmartConnect and routed that back to my PS block for the sake of tying off everything. However, with that done, get the following critical warnings:

  •  [xilinx.com:ip:smartconnect:1.0-1] top_smartconnect_0_0: RUSER_WIDTH (1) of S00_AXI must be integer number of bits per byte of RDATA (64).
    [xilinx.com:ip:smartconnect:1.0-1] top_smartconnect_0_0: WUSER_WIDTH (1) of S00_AXI must be integer number of bits per byte of WDATA (64).
    [xilinx.com:ip:smartconnect:1.0-1] top_smartconnect_0_0: RUSER_WIDTH (1) of S01_AXI must be integer number of bits per byte of RDATA (64).
    [xilinx.com:ip:smartconnect:1.0-1] top_smartconnect_0_0: WUSER_WIDTH (1) of S01_AXI must be integer number of bits per byte of WDATA (64).
    [xilinx.com:ip:smartconnect:1.0-1] top_smartconnect_0_0: RUSER_WIDTH (1) of S02_AXI must be integer number of bits per byte of RDATA (64).
    [xilinx.com:ip:smartconnect:1.0-1] top_smartconnect_0_0: WUSER_WIDTH (1) of S02_AXI must be integer number of bits per byte of WDATA (64).

 

 

m_axi_channels.png

This is pretty cryptic? What does it mean, and how can I fix it?

(I already tried manually overriding the data widths in the SmartConnect config screen, but not of my changes stick after I hit OK.)

4 Replies
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Observer
Observer
152 Views
Registered: ‎05-04-2018

Re: SmartConnect configuration problem / AXI master tie-off

I have the same problem, anyone has a solution?

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Scholar
Scholar
125 Views
Registered: ‎05-21-2015

Re: SmartConnect configuration problem / AXI master tie-off

@joelschad, @wadelius ,

The xUSER signals are optional signals.  You don't need them, and should be able to remove them from an interface.

It appears as though the problem in this case is that the transaction needs to go through a resizing operation.  Which of the resized beats should then contain the xUSER bits?  It's not clear.  Since the signals are optional, removing them should (again) fix this issue.

Dan

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Observer
Observer
74 Views
Registered: ‎05-04-2018

Re: SmartConnect configuration problem / AXI master tie-off

Hi thanks for response

How do I remove them in a block design when it is between two Xilinx IP cores?

/Urban

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Xilinx Employee
Xilinx Employee
23 Views
Registered: ‎10-12-2018

Re: SmartConnect configuration problem / AXI master tie-off

Hi All,

As described in the SmartConnect product guide PG247, chapter 3, section “User Defined Signal Propagation” the ruser and wuser signals provided to smatconnect must be sized in a bit-mutilple of the number of bytes of data carried on the interface.

Smartconnect does not transport ruser or wuser signals that do not meet this requirement, hence the critical warning issued by the IP during validation of this design. This is a new feature of smartconnect and is not available in the older AXI interconnect IP.

Please repackage to remove user bit ports or align the ruser/wuser ports to datawidth/8.

Thanks & Regards
Anil B
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