10-10-2019 01:43 PM
I am using vivado 2019.1 and an UltraScale+ SoC.
I am using a Video Mixer block configured for 3 overlay layers. Configuring for overlay layers creates an AXI master output on the Video Mixer block for each such layer.
At the beginning, I ignored the AXI master outs on this block, but design validation threw some warnings, so I ran the AXI masters to a SmartConnect and routed that back to my PS block for the sake of tying off everything. However, with that done, get the following critical warnings:
This is pretty cryptic? What does it mean, and how can I fix it?
(I already tried manually overriding the data widths in the SmartConnect config screen, but not of my changes stick after I hit OK.)
05-08-2020 08:46 AM
The xUSER signals are optional signals. You don't need them, and should be able to remove them from an interface.
It appears as though the problem in this case is that the transaction needs to go through a resizing operation. Which of the resized beats should then contain the xUSER bits? It's not clear. Since the signals are optional, removing them should (again) fix this issue.
05-11-2020 01:03 AM
Hi thanks for response
How do I remove them in a block design when it is between two Xilinx IP cores?
05-25-2020 11:53 PM
As described in the SmartConnect product guide PG247, chapter 3, section “User Defined Signal Propagation” the ruser and wuser signals provided to smatconnect must be sized in a bit-mutilple of the number of bytes of data carried on the interface.
Smartconnect does not transport ruser or wuser signals that do not meet this requirement, hence the critical warning issued by the IP during validation of this design. This is a new feature of smartconnect and is not available in the older AXI interconnect IP.
Please repackage to remove user bit ports or align the ruser/wuser ports to datawidth/8.