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jliu83
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Registered: ‎06-26-2008

Strange Behavior with Xilinx Video Timing Controller (VTC)

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I'd like to generate timing controls dynamically, but the generator instance of my VTC is acting very strangely.  I cannot deviate the timing control signals beyond the default values.

 

In XPS the instance is configured very simply:

 

BEGIN v_tc
PARAMETER INSTANCE = vid_out_vtc
PARAMETER HW_VER = 5.01.a
PARAMETER C_MAX_PIXELS = 2048
PARAMETER C_MAX_LINES = 2048
PARAMETER C_BASEADDR = 0x75800000
PARAMETER C_HIGHADDR = 0x7580ffff
PARAMETER C_GEN_VIDEO_FORMAT = 2
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE VTIMING_OUT = vid_out_vtc_VTIMING_OUT
PORT s_axi_aclk = clk_133_3333MHz
PORT clk = clk_axi_dcm_clkgen_0CLKFX_OUT
PORT gen_clken = vid_out_vtg_ce
END

 

I followed the API's instructions to initialize the unit:

 

//configure
VtcOutConfig = XVtc_LookupConfig(XPAR_VTC_1_DEVICE_ID);
XVtc_CfgInitialize(&VtcOut, VtcOutConfig, VtcOutConfig->BaseAddress);

//set Polarity
pol.HBlankPol = 1;
pol.HSyncPol = 1;
pol.VBlankPol = 1;
pol.VSyncPol = 1;
pol.ActiveChromaPol = 1;
pol.ActiveVideoPol = 1;
xil_printf("Setting Vtc out Polarity\r\n);
XVtc_SetPolarity(&VtcOut, &pol);

//set source
src.ActiveVideoPolsrc=1;
src.ActiveChromaPolsrc=1;
src.HSyncPolsrc=1;
src.HBlankPolsrc=1;
src.HBackPorchsrc=1;
src.HFrontPorchsrc=1;
src.HSyncsrc=1;
src.HActivesrc=1;
src.HTotalsrc=1;
src.VSyncPolsrc=1;
src.VBlankPolsrc=1;
src.VBackPorchsrc=1;
src.VFrontPorchsrc=1;
src.VSyncsrc=1;
src.VActivesrc=1;
src.VTotalsrc=1;
xil_printf("Setting Vtc out Source \r\n");
XVtc_SetSource(&VtcOut, &src);

//THIS PART HAS NO EFFECT//
//set 720p output
sig.OriginMode = 0;
sig.HActiveStart = 0;
sig.HFrontPorchStart = 1280;
sig.HSyncStart = 1344;
sig.HBackPorchStart = 1430;
sig.HTotal = 1390;
sig.V0ActiveStart = 0;
sig.V0FrontPorchStart = 720;
sig.V0SyncStart = 724;
sig.V0BackPorchStart = 729;
sig.V0Total = 750;

XVtc_SetGenerator(&VtcOut, &sig);
//END PART WITH NO EFFECT//

xil_printf("Setting Vtc out Enable\r\n");
XVtc_Enable(&VtcOut, XVTC_EN_GENERATOR);

 

 

 Here's the strange part, when I call the XVtc_Enable signal, the default timing starts, but no matter how I configure the generator signal using XVtc_SetGenerator, the output remains the same.  I have tried XVtc_Disable, changing the generator signal, then XVtc_Enable, as well as XVtc_Reset before changing the signal, but to no avail.  I have checked the return on all the functions called to make sure that the return status is XST_SUCCESS.  No matter what I put in the initialization to the &sig variable, the output is always the same (resulting in the default timing specified in XPS).  I need to be able to change these values to something other than the default.  Am I forgetting something simple?

 

Thanks,

-J

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bwiec
Xilinx Employee
Xilinx Employee
4,703 Views
Registered: ‎08-02-2011
Can you check to see if the reg_update bit in the control register is being updated by XVtc_Enable. I can't recall off hand if that function sets it or if there is another function call necessary.
www.xilinx.com

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bwiec
Xilinx Employee
Xilinx Employee
4,704 Views
Registered: ‎08-02-2011
Can you check to see if the reg_update bit in the control register is being updated by XVtc_Enable. I can't recall off hand if that function sets it or if there is another function call necessary.
www.xilinx.com

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jliu83
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Registered: ‎06-26-2008

You are right, the timing registers are double buffered.  A called to update the register must be explicitly invoked.

 

Very obscure in the documentation on pg016_v_tc.pdf, Page 33, under REG_UPDATE.  The API does not mention the register in the sequence of initialization.  I needed to call the macro:

 

//update Registers
XVtc_RegUpdate(&VtcOut);

 The VTC now changes frequency, but the Syncs are irregular.  Is XVtc_Reset requried to produce regular syncs?

 

-J

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jliu83
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Registered: ‎06-26-2008

Seems like the VDMA output signal stride length must match the timing information on the VTC, otherwise, there's a premature vsync that is outputted and the Video Output will not lock.  The IP's are functionning correctly.  Thank you for the help.

 

-J

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