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anggapp
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Registered: ‎09-28-2016

Stream Data from DMA to GPIO

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Hello, newbie here..

So I'm using Xilinx Vivado 2014.2 to design system to send datas from MATLAB in PC to ZYBO through Ethernet, then send those data to pin out to be modulated using DAC. 
First, I had successfully designed the system to send received data from Ethernet in PS to AXI Interconnect, then to AXI GPIO. The modulated signal are fine, it modulate the digital data that was sent from MATLAB. The problem is the signal frequency are not fast enough. I have known that using AXI GPIO IP won't give a high throughput to the system. The project requirement is to modulate signal in (min.) 1 MHz frequency

Then I'm using DMA to send the data from PS to DMA MM2S port, to AXI Stream Data FIFO then to AXI Register Slice then to output pin. This is my block design

design 01.PNG

 

[Please correct me if I am wrong.. :) ]

 

Using this design, I've checked the received data in PS from Ethernet connection by print it on the Xilinx SDK console and the received datas are correct. But the datas can't be sent correctly to the output pin.

I am using SendPacket function in the DMA Library to send the datas and have checked all the constraint pin in the Vivado design. No matter what datas are sent from the MATLAB, the 10 bit output in the pinout on ZYBO are always '0011010100' (I've  checked it using multimeter) even if the datas that printed on the console are correct.


So what should I do to stream the data to the output pin correctly?
Thanks before.

 

 

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bwiec
Xilinx Employee
Xilinx Employee
8,960 Views
Registered: ‎08-02-2011

Hello,

 

Your hardware setup looks reasonable to me. Though you probably don't need to use the Scatter Gather engine (I don't see the need based on your description, anyway).

 

On the software side, one thing that catches a lot of people in this scenario is caching. Make sure you flush your cache once you fill the buffer that's going to be DMA'd.

 

If that doesn't help, I'd use the 'Mark Debug' option in IP Integrator to tag the DMA's interfaces and follow the data along to see where it gets corrupted.

 

I always point people to these designs as a good starting point for the AXI DMA:

http://www.xilinx.com/support/answers/57550.html

www.xilinx.com

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bwiec
Xilinx Employee
Xilinx Employee
8,961 Views
Registered: ‎08-02-2011

Hello,

 

Your hardware setup looks reasonable to me. Though you probably don't need to use the Scatter Gather engine (I don't see the need based on your description, anyway).

 

On the software side, one thing that catches a lot of people in this scenario is caching. Make sure you flush your cache once you fill the buffer that's going to be DMA'd.

 

If that doesn't help, I'd use the 'Mark Debug' option in IP Integrator to tag the DMA's interfaces and follow the data along to see where it gets corrupted.

 

I always point people to these designs as a good starting point for the AXI DMA:

http://www.xilinx.com/support/answers/57550.html

www.xilinx.com

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anggapp
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Registered: ‎09-28-2016

Thanks for your reply @bwiec.

It turns out that the fault is on software. I set the buffer size wrong. Now the data from ethernet can be outputted to the GPIO rightfully. Oh and you're right, I don't need to use the scatter gather engine based on the requirement.

Now the problem is the frequency of the output data is too slow, around 30 Hz. It's even faster if I am using AXI GPIO block without DMA, around 100 Hz.
I think the problem is because I am using single packet transmission by setting sendpacket function like this

static int SendPacket(XAxiDma * AxiDmaInstPtr)
{
	XAxiDma_BdRing *TxRingPtr;
	u32 *TxPacket;
	XAxiDma_Bd *BdPtr;
	int Status;
	int Index = 0;

	TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);

	/* Create pattern in the packet to transmit */
	TxPacket = (u8 *) Packet;

//	memcpy(TxPacket,&TxTemp[1],LUT_LENGTH*4);
	TxPacket[Index] = TxTemp[Ind];

//	xil_printf("%d\n", TxPacket[Index]);


	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
	 * is enabled
	 */
	Xil_DCacheFlushRange((u32)TxPacket, 1);


	/* Allocate a BD */
	Status = XAxiDma_BdRingAlloc(TxRingPtr, 1, &BdPtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/* Set up the BD using the information of the packet to transmit */
	Status = XAxiDma_BdSetBufAddr(BdPtr, (u32) Packet);
	if (Status != XST_SUCCESS) {
		xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
		    (unsigned int)Packet, (unsigned int)BdPtr, Status);

		return XST_FAILURE;
	}

	Status = XAxiDma_BdSetLength(BdPtr, 1,
				TxRingPtr->MaxTransferLen);
	if (Status != XST_SUCCESS) {
		xil_printf("Tx set length %d on BD %x failed %d\r\n",
		    MAX_PKT_LEN, (unsigned int)BdPtr, Status);

		return XST_FAILURE;
	}

#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
	Status = XAxiDma_BdSetAppWord(BdPtr,
	    XAXIDMA_LAST_APPWORD, MAX_PKT_LEN);

	/* If Set app length failed, it is not fatal
	 */
	if (Status != XST_SUCCESS) {
		xil_printf("Set app word failed with %d\r\n", Status);
	}
#endif

	/* For single packet, both SOF and EOF are to be set
	 */
	XAxiDma_BdSetCtrl(BdPtr, XAXIDMA_BD_CTRL_TXEOF_MASK |
						XAXIDMA_BD_CTRL_TXSOF_MASK);

	XAxiDma_BdSetId(BdPtr, (u32) Packet);

	/* Give the BD to DMA to kick off the transmission. */
	Status = XAxiDma_BdRingToHw(TxRingPtr, 1, BdPtr);
	if (Status != XST_SUCCESS) {
		xil_printf("to hw failed %d\r\n", Status);
		return XST_FAILURE;
	}

	return XST_SUCCESS;
}

 

Is there any way to make the output data frequency faster?
If I only use Block Design, without software, by using the data that is stored in LUT, the output frequency can achieve high speed, 1 MHz++. But then, I can't get the data from ethernet.

 

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