Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎02-27-2013

Swapping DQ Bytes and Bits within a Byte



What is the software impact of swapping the DDR bytes lanes and the bits within the lanes on the Zynq?  The goal is to avoid writing custom low-level software for the board and take advantage of the existing FSBL and Linux kernel.


I am working on a LPDDR2 design using a 32-bit Micron MT42L128M32D1 and noticed in UG933 that such swapping is permissible, but have not found any configuration within PlanAhead/ISE/Vivando for configuring the revised order.  Unfortunately I am afraid that means some low level driver work is required for this general statement to be true to allow for when MODE REGISTER READ command is issued.


For actual data bytes it does not matter, but the LSB order might always need be the LSB for the ZQ calibration sequence that reads & writes specific sequences.  Addtionally,  reading the MODE registers output on DQ[7:0].  Writing the MODE registers only requires the CMD/CA lines, so that will be unaffected.


I have never swapped the order before and want to make sure there is not a software effort also required.  If the issues in the previous paragraph are the only ones, I can keep DQ[7:0] in order and at Byte0 while reording the other 3 bytes.  Maybe the MRR command is unused in any implementation and that point is irrelevant?




0 Kudos
2 Replies
Registered: ‎08-14-2007

As you already pointed out, the Mode register only uses address bits, not data bits.  In fact

the reason you cannot swap address bits is in part due to the Mode register.  The other reason

is that the lower address bits (up to the burst size) form a counter within the memory chip.

There is nothing special about data bits or bytes, and nothing comes from them that wasn't first

written to them, so the order is not restricted except to keep the bits with a byte associated with

the correct DQS and DM signals.


Generally for newer devices with hard memory controllers, the swapping must be done at

the board layout level without telling the tools to change the bit numbering.  i.e. your FPGA

design will still use the originally assigned pins, but they may hook to a DRAM pin with a different

name on the memory chip.  This will not affect software.


-- Gabor

-- Gabor
0 Kudos
Xilinx Employee
Xilinx Employee
Registered: ‎09-21-2011



Please refer to this thread as it is dealing with the same topic on LPDDR2:





0 Kudos