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Observer
Observer
8,096 Views
Registered: ‎09-11-2015

System cache with Microblaze not playing coherency

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Hello,

 

I have an XPS 14.4 project with quad core microblazes. All data_cache ports are connected to System cache.

BEGIN system_cache
 PARAMETER INSTANCE = system_cache_0
 PARAMETER HW_VER = 1.01.c
 PARAMETER C_M_AXI_DATA_WIDTH = 128
 PARAMETER C_NUM_OPTIMIZED_PORTS = 4
 PARAMETER C_CACHE_SIZE = 65536
 PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC
 PARAMETER C_INTERCONNECT_S1_AXI_MASTERS = microblaze_1.M_AXI_DC
 PARAMETER C_INTERCONNECT_S2_AXI_MASTERS = microblaze_2.M_AXI_DC
 PARAMETER C_INTERCONNECT_S3_AXI_MASTERS = microblaze_3.M_AXI_DC
 PARAMETER C_BASEADDR = 0xa8000000
 PARAMETER C_HIGHADDR = 0xafffffff
 BUS_INTERFACE M_AXI = axi4_0
 BUS_INTERFACE S0_AXI = mb_axi4_DC0
 BUS_INTERFACE S1_AXI = mb_axi4_DC1
 BUS_INTERFACE S2_AXI = mb_axi4_DC2
 BUS_INTERFACE S3_AXI = mb_axi4_DC3
 PORT ACLK = clk_100_0000MHzPLL0
END

Simple mem_test pass for all cores. But data written from a core is not read by another! The below code executes on all cores, all of them reach the error/timeout state. At lease I expect 3 of four to get unlocked properly.

 

    enable_caches();
int i=0; volatile u8* pNoWhere = (u8*)0xa8ff3344; // inside cached SDRAM *pNoWhere = getCoreID(); //from PVR reg while(*pNoWhere == getCoreID()){ DelayWithID(); //each core gets a different delay if(++i>10){ xil_printf("Error at:"); break; } } xil_printf("Core-%d sync! \n\r",getCoreID()); //System Cache Works!

Do I need to make any action at the system cache control bus?

Did I miss an option at the MHS system cache entry?

C-Code problem?

 

Appreciate your support,

 

Tarek

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Observer
Observer
15,033 Views
Registered: ‎09-11-2015

Fixed!

 

The learned lesson: Enabling CPU D-cache causes non-working L2 cache

//Xil_DCacheEnable(); 

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Observer
Observer
15,034 Views
Registered: ‎09-11-2015

Fixed!

 

The learned lesson: Enabling CPU D-cache causes non-working L2 cache

//Xil_DCacheEnable(); 

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Xilinx Employee
Xilinx Employee
7,664 Views
Registered: ‎08-06-2007

Hi,

 

If you don't enable cache coherency both on the System Cache and MicroBlaze, you can't use caches on MicroBlazes which you have discovered.

 

Enable MicroBlaze cache coherency (only works with write-through caches):

Set the configuration "C_INTERCONNECT = 3" which is the ACE bus interface.

 

Enable System Cache cache coherency:

Set the configuration "C_ENABLE_COHERENCY = 1"

 

Göran

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Observer
Observer
7,313 Views
Registered: ‎09-11-2015

@goran Thanks, but my microblaze version does not have an ACE interface. As far as I know, WRITE_THROUGH is the default cache policy. So what do I miss in microblaze 8.40?

 

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Xilinx Employee
Xilinx Employee
7,309 Views
Registered: ‎08-06-2007

Hi,

 

So you want to use the SystemCache and MicroBlaze caches but not having MicroBlaze cache coherency?

If so, you need to handle all coherency issues in software to make sure that the System Cache and MicroBlaze caches are updated correctly.

Just having Write-Through caches is not enough since one MicroBlaze cache will not be aware that someone else has updated the same data location (snooping => which is a big part of the coherency scheme).

 

Göran

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