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toshas
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Registered: ‎02-14-2009

TVCCO2VCCAUX for Zynq MPSOC

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Hi!

 

For Zynq 7000 there was recommended power supply sequencing (ds191):

"The recommended power-on sequence for the PL is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the
same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels
then they can be powered by the same supply and ramped simultaneously."

  

With special note about HR bank:

"For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
• The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
• The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps."

 

Also this parameter was described in AR44225 and AR37347:

"for VCCO voltages of 3.3V in HR I/O banks and configuration bank 0, 
the voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX
for each power-on/off cycle to maintain device reliability levels."


Now MPSOC devices is available. ds925 has same power-up sequence:

"The recommended power-on sequence is VCCINT,  VCCINT_IO/VCCBRAM, VCCINT_VCU, VCCAUX/VCCAUX_IO, and VCCO 
to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.
The recommended power-off sequence is the reverse of the power-on sequence.
If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels,
they can be powered by the same supply and ramped simultaneously.
VCCINT_IO must be connected to VCCBRAM.
If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels,
they can be powered by the same supply and ramped simultaneously.
VCCAUX and VCCAUX_IO must be connected together.
VCCADC and VREF can be powered at any time and have no power-up sequencing requirements."

 

But now there is no note about VCCO/VCCAUX behaviour in case when VCCO is applied first or start is simultaneous.

 

Which times and voltage levels are specified for this case (when we are talking about HD banks of Zynq MPSOC) ?

Is it the same (2.625V / TVCCO2VCCAUX) or not ?

 

Thanks!

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austin
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Registered: ‎02-27-2008

Zynq MPSoC,

 

Does NOT have the same restriction as Zynq regarding the Vcco sequencing voltage levels.

 

So, as documented, you are encouraged to follow the stated sequence. Other sequences work just fine, but startup current and IO behavior is not guaranteed as documented (data sheet only applies to the sequence noted).  The startup current may be slightly more (or less) on any given rail, and the IO may assert briefly (not be tristate) with a different sequence.  If that is OK in your application, then no problem.

 

All at once (no sequencing) works just fine as well, however, all devices get tested for the sequence in the data sheet.  To test all other possible sequences would just take too long to be practical.  We did that in characterization to specifically identify any prohibited sequences, but there are no prohibited sequences in UltraScale+.

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
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2,595 Views
Registered: ‎02-27-2008

Zynq MPSoC,

 

Does NOT have the same restriction as Zynq regarding the Vcco sequencing voltage levels.

 

So, as documented, you are encouraged to follow the stated sequence. Other sequences work just fine, but startup current and IO behavior is not guaranteed as documented (data sheet only applies to the sequence noted).  The startup current may be slightly more (or less) on any given rail, and the IO may assert briefly (not be tristate) with a different sequence.  If that is OK in your application, then no problem.

 

All at once (no sequencing) works just fine as well, however, all devices get tested for the sequence in the data sheet.  To test all other possible sequences would just take too long to be practical.  We did that in characterization to specifically identify any prohibited sequences, but there are no prohibited sequences in UltraScale+.

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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toshas
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Registered: ‎02-14-2009

Hi!

 

Thanks for the quick reply!

 

In other words, just to be clear:

 

We are talking only about HD banks on Zynq MPSOC.
Is it possible to have Vcco (3.3V) turned on before (with let's say 10s delay) other supply voltages (Vccint,Vccaux) ?
It will not lead to device damage (IO state behaviour does not matter now), isn't it ?

 

Thanks!

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austin
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Registered: ‎02-27-2008

No,

 

The Vcco, Vccaux sequence MUST be observed to prevent damage in 7 series (Zynq 7000 parts are 7 series devices).

 

(part of your original post).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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toshas
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Registered: ‎02-14-2009

For Zynq 7000 it's clear, but thread is about Zynq Ultrascale+ MPSOC.

 

Is it safe for new Zynq ?

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austin
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Registered: ‎02-27-2008

Yes,

 

And as I posted Zynq MPSoC does NOT have the restriction in the data sheet.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
toshas
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Registered: ‎02-14-2009

Thanks a lot!

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