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dimitris78
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Registered: ‎09-13-2019

Throughput of AXI interconnect

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I have an AXI interconnect that connects 8 masters to 2 slaves. Consider masters #3 - 8 to be idle during the phase of operation. Can master #1 be writing to slave #1 at full throughput, when master #2 is reading from slave #2 at the same time at full throughput ?

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dgisselq
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Registered: ‎05-21-2015

@dimitris78,

That depends upon how you have it configured.

Xilinx's interconnect has two configurations or modes of operation.  One allows only one downstream address (ARADDR == AWADDR across all slaves) and so only ever routes one transaction downstream at a time.  This is an area constrained crossbar.  A second configuration is a full crossbar, which should be able to support multiple concurrent connections through it at the same time.

Do be aware, Xilinx's demo slaves will exhibit their faults in the full configuration, halting/freezing the bus by dropping packets, but not in the single address configuration.

Dan

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dgisselq
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Registered: ‎05-21-2015

@dimitris78,

That depends upon how you have it configured.

Xilinx's interconnect has two configurations or modes of operation.  One allows only one downstream address (ARADDR == AWADDR across all slaves) and so only ever routes one transaction downstream at a time.  This is an area constrained crossbar.  A second configuration is a full crossbar, which should be able to support multiple concurrent connections through it at the same time.

Do be aware, Xilinx's demo slaves will exhibit their faults in the full configuration, halting/freezing the bus by dropping packets, but not in the single address configuration.

Dan

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dimitris78
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Registered: ‎09-13-2019

hi @dgisselq ,

I looked up the cross-bar mode that you mentioned:

https://www.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v2_1/pg059-axi-interconnect.pdf

It's mentioned in page 6 and then pages 14 and 15 again. It's clear that's what is needed, I do have a side question however.

I'm using the AXI interconnect IP which i now configured as "performance optimized", which according to the document should implement the cross-bar mode.

I also looked up the AXI crossbar IP, and I it has a lot more explicit configuration. 

Just to see if my understanding is correct: they both do the same thing. it's just that the cross-bar is more configurable, right ?

 

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dgisselq
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Registered: ‎05-21-2015

If I understand properly, the interconnect includes a crossbar within it.

Dan