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ivkome
Observer
Observer
312 Views
Registered: ‎04-21-2021

[Timing 38-282] The design failed to meet the timing requirements.

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Hello ,

i'm introducing myself with Vivado to work with my FPGA-Board. By trying to design and compile the DBs. I receive the following failure, that i'm unable to resolve. I attach my design and failure.

Please help me to identify, what i did wrong. Thanks !

 

 

2021-04-29_11h37_29.png2021-04-29_11h39_52.png

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bruce_karaffa
Scholar
Scholar
287 Views
Registered: ‎06-21-2017

First, the name of the clock, clk_200MHz_p would typically indicate a differential input clock.  Is your clock input differential, something like LVDS?  If so, you must use a differential input buffer, an IBUFDS) to receive it and turn it into a single ended signal to use in the FPGA fabric.  Second, are you sending the input clock through a clock wizard (an MMCM with appropriate clock buffers)?  At 200MHz, you need a proper clocking structure.  Third, does your clock come into the FPGA on a clock capable pin?  These pins will have "gc" as part of the pin name.

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3 Replies
richardhead
Scholar
Scholar
303 Views
Registered: ‎08-01-2012

Did you check the timing report for details on the timing violations?

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ivkome
Observer
Observer
290 Views
Registered: ‎04-21-2021

Hello @scholar ,

thanks for your reply. Well, i could find out the following some information concerning the timing violations (See Screenshot). But to be honest, i can't understand, what to do.

 

 

 

2021-04-29_12h50_19.png

2021-04-29_12h50_52.png

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bruce_karaffa
Scholar
Scholar
288 Views
Registered: ‎06-21-2017

First, the name of the clock, clk_200MHz_p would typically indicate a differential input clock.  Is your clock input differential, something like LVDS?  If so, you must use a differential input buffer, an IBUFDS) to receive it and turn it into a single ended signal to use in the FPGA fabric.  Second, are you sending the input clock through a clock wizard (an MMCM with appropriate clock buffers)?  At 200MHz, you need a proper clocking structure.  Third, does your clock come into the FPGA on a clock capable pin?  These pins will have "gc" as part of the pin name.

View solution in original post