I have an original design with XXV Ethernet and AXI DMA on my Zynq MPSoC platform, which works well. And now I'm evaluating the MCDMA solution. The design is modified simply to replace AXI DMA to MCDMA.
The new design has timing violations in MCDMA while implementing in Vivado 2018.3. However it can be successfully implemented in Vivado 2019.2 without timing issue.
Any idea how to solve the issue in Vivado 2018.3? Or what action shall I take to further locate the root cause?
Timing report and BD TCL files of AXI DMA and MCDMA are attached.