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Participant
Participant
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Registered: ‎03-01-2017

Timing constrain failed

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Hello,

 

I am trying to figure out how to fix a timing constrain error by looking at the Post-PAR static Timing Report. One of the failure is :

 

 

Slack:                  -3.393ns (requirement - (data path - clock path skew + uncertainty))
  Source:               disparity_fpga_calculations_0/disparity_fpga_calculations_0/USER_LOGIC_I/buffer0_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP (RAM)
  Destination:          disparity_fpga_calculations_0/disparity_fpga_calculations_0/USER_LOGIC_I/buffer2_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP (RAM)
  Requirement:          10.000ns
  Data Path Delay:      13.458ns (Levels of Logic = 10)
  Clock Path Skew:      0.146ns (1.623 - 1.477)
  Source Clock:         clk_100_0000MHzPLL0_ADJUST rising at 0.000ns
  Destination Clock:    clk_100_0000MHzPLL0_ADJUST rising at 10.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.146ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: disparity_fpga_calculations_0/disparity_fpga_calculations_0/USER_LOGIC_I/buffer0_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP to disparity_fpga_calculations_0/disparity_fpga_calculations_0/USER_LOGIC_I/buffer2_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP

 

This is part of a custom peripheral with user memory. 

 

buffer0_inst and buufer2_inst are two instances of bram generated by core generator. 

 

So is it complaining about the path between buffer0 and buffer2 ? There shouldn't be any direct path between the two pieces of bram. The only path between the two brams is through a module, which connects to these two brams.

 

How should I go about fixing this timing error ?

 

Thank you very much for any comments.

 

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Guide
Guide
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Registered: ‎01-23-2009

You haven't given us much to go on - you only showed the header of the timing report, not the complete timing report.

 

A path starts at a clocked startpoint, ends at a clocked endpoint, and goes through all the combinatorial cells and nets between them. In this case your startpoint and endpoint are RAMs, and presumably your module between them is all combinatorial cells (i.e. there are no flip-flops in the module between the RAMs) - the report says there are 10 levels of logic (i.e. 10 levels of LUTs or other cells) between them.

 

From the naming conventions alone, it looks like these RAMs are large - the "ramloop[36]" hints that there are at least 36 RAMs in the group of RAMs for the startpoint. Really large RAMs are terrible for timing - take a look at this post on large RAMs and their impact on timing.

 

Even assuming the RAMs are reasonable sized, paths that go from RAM to RAM tend to be a problem both due to the fact that RAMs are fairly far apart and the "clock to output" of a RAM is quite large. In general paths like this need to be pipelined - possibly several times - in order to get them to meet timing...

 

Avrum

 

 

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Highlighted
Guide
Guide
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Registered: ‎01-23-2009

You haven't given us much to go on - you only showed the header of the timing report, not the complete timing report.

 

A path starts at a clocked startpoint, ends at a clocked endpoint, and goes through all the combinatorial cells and nets between them. In this case your startpoint and endpoint are RAMs, and presumably your module between them is all combinatorial cells (i.e. there are no flip-flops in the module between the RAMs) - the report says there are 10 levels of logic (i.e. 10 levels of LUTs or other cells) between them.

 

From the naming conventions alone, it looks like these RAMs are large - the "ramloop[36]" hints that there are at least 36 RAMs in the group of RAMs for the startpoint. Really large RAMs are terrible for timing - take a look at this post on large RAMs and their impact on timing.

 

Even assuming the RAMs are reasonable sized, paths that go from RAM to RAM tend to be a problem both due to the fact that RAMs are fairly far apart and the "clock to output" of a RAM is quite large. In general paths like this need to be pipelined - possibly several times - in order to get them to meet timing...

 

Avrum

 

 

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Participant
Participant
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Registered: ‎03-01-2017

Thank you very much for the reply.

 

Looking deeper at the report suggested that there are too much combinational circuit between the two brams. Output from one of the bram is used to calculated to address to another bram.

 

I reduced the amount of combinational logic and the timing has passed.

 

 

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