10-15-2020 04:30 AM
10-19-2020 01:57 AM
10-20-2020 07:39 PM - edited 10-21-2020 07:44 AM
10-21-2020 12:24 AM
I recently found a number of limitations of the DMA IP core. I solved it with a piece of HLS and an AXI master port interfacing the memory AXI slave. Not difficult and you have more control. My suggestion is that you implement it in HLS, it's an AXI-stream on one side, AXI master on the other, and some logic and buffer in between.
10-21-2020 02:27 AM
I'm not aware of any ref design specific for that. I got everything from UG902 basically. the key thing is configuring the ports, besides that I think it's a simple thing: receive via stream and save sequentially. You may want to read Tlast to end the transfer and reset the write pointer, etc.
10-21-2020 02:32 AM
With HLS you can have a smarter solution, first of all you don't need software to set it up, second you can have, for example, the transfer size at the start of the stream so the IP knows when to stop. Even possible for the IP to stop if, for example, no data for N clocks. I used the DMA blocks a lot, but they are limited. I read somewhere if they receive data before set up, they hang.