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Participant
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Registered: ‎08-28-2020

Transfer data from DRAM and PS cache to PL simultenously

I'm trying to design an architecture where I have to transfer data from PS cache to PL and at the same time data from DRAM needs to be transferred to PL. In this case data in PS cache needs to be transferred to one FIFO and DRAM data needs to be transferred to another FIFO.

Following details are my considerations for this architecture.

1. PS can access PL through GP port. Since AXI data mover supports MM2S channel, AXI data mover can be used to transfer PS cache data to PL side fifo.

2. AXI DMA can access DRAM using HP port. Therefore to transfer data from DRAM to FIFO, I'm going to configure MM2S channel to transfer data from DRAM to other FIFO in PL side.

Therefore, I believe PL can be accessed through both HP and GP ports simultaneously to transfer data from DRAM to PL and PS cache to PL.

Can anyone please explain if there's any issue with above architecture? Or if it's correct please inform that too.

If there's any efficient method rather than above method please inform that too. Thank you for your support.

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